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[Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but no
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode |
Date: |
Tue, 25 Sep 2018 14:41:44 +0100 |
The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 258ba6dcaad..b5e61cc1775 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -199,8 +199,18 @@ static void arm_cpu_reset(CPUState *s)
env->cp15.c15_cpar = 1;
}
#else
- /* SVC mode with interrupts disabled. */
- env->uncached_cpsr = ARM_CPU_MODE_SVC;
+
+ /*
+ * If the highest available EL is EL2, AArch32 will start in Hyp
+ * mode; otherwise it starts in SVC. Note that if we start in
+ * AArch64 then these values in the uncached_cpsr will be ignored.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ !arm_feature(env, ARM_FEATURE_EL3)) {
+ env->uncached_cpsr = ARM_CPU_MODE_HYP;
+ } else {
+ env->uncached_cpsr = ARM_CPU_MODE_SVC;
+ }
env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
if (arm_feature(env, ARM_FEATURE_M)) {
--
2.19.0
- [Qemu-devel] [PULL 18/21] hw/arm/aspeed: change the FMC flash model of the AST2500 evb, (continued)
- [Qemu-devel] [PULL 18/21] hw/arm/aspeed: change the FMC flash model of the AST2500 evb, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 04/21] MAINTAINERS: Add NRF51 entry, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 02/21] hw/arm/exynos4210: fix Exynos4210 UART support, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 01/21] target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 20/21] aspeed/smc: fix some alignment issues, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 05/21] arm: Add Nordic Semiconductor nRF51 SoC, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 19/21] hw/arm/aspeed: Add an Aspeed machine class, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 06/21] arm: Add BBC micro:bit machine, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 16/21] hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 08/21] aspeed/i2c: Handle receive command in separate function, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode,
Peter Maydell <=
- [Qemu-devel] [PULL 11/21] hw/arm/smmuv3: fix eventq recording and IRQ triggerring, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 07/21] aspeed/i2c: interrupts should be cleared by software only, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 13/21] hw/intc/arm_gic: Drop GIC_BASE_IRQ macro, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 15/21] hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 12/21] hw/intc/arm_gic: Document QEMU interface, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 10/21] hw/arm/smmu-common: Fix the name of the iommu memory regions, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 09/21] aspeed/i2c: Fix receive done interrupt handling, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 17/21] aspeed/timer: fix compile breakage with clang 3.4.2, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 14/21] hw/net/pcnet-pci: Convert away from old_mmio accessors, Peter Maydell, 2018/09/25