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[Qemu-devel] [PULL 09/21] aspeed/i2c: Fix receive done interrupt handlin
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/21] aspeed/i2c: Fix receive done interrupt handling |
Date: |
Tue, 25 Sep 2018 14:41:32 +0100 |
From: Guenter Roeck <address@hidden>
The AST2500 datasheet says:
I2CD10 Interrupt Status Register
bit 2 Receive Done Interrupt status
S/W needs to clear this status bit to allow next data receiving
The Rx interrupt done interrupt status bit needs to be cleared
explicitly before the next byte can be received, and must therefore
not be auto-cleared. Also, receiving the next byte must be delayed
until the bit has been cleared.
Signed-off-by: Guenter Roeck <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/i2c/aspeed_i2c.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index ce16efc1367..a2dfa827604 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -252,7 +252,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus,
uint64_t value)
aspeed_i2c_set_state(bus, I2CD_MACTIVE);
}
- if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
+ if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
+ !(bus->intr_status & I2CD_INTR_RX_DONE)) {
aspeed_i2c_handle_rx_cmd(bus);
}
@@ -274,6 +275,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr
offset,
uint64_t value, unsigned size)
{
AspeedI2CBus *bus = opaque;
+ bool handle_rx;
switch (offset) {
case I2CD_FUN_CTRL_REG:
@@ -294,11 +296,17 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr
offset,
bus->intr_ctrl = value & 0x7FFF;
break;
case I2CD_INTR_STS_REG:
+ handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
+ (value & I2CD_INTR_RX_DONE);
bus->intr_status &= ~(value & 0x7FFF);
if (!bus->intr_status) {
bus->controller->intr_status &= ~(1 << bus->id);
qemu_irq_lower(bus->controller->irq);
}
+ if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
+ aspeed_i2c_handle_rx_cmd(bus);
+ aspeed_i2c_bus_raise_interrupt(bus);
+ }
break;
case I2CD_DEV_ADDR_REG:
qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
--
2.19.0
- [Qemu-devel] [PULL 06/21] arm: Add BBC micro:bit machine, (continued)
- [Qemu-devel] [PULL 06/21] arm: Add BBC micro:bit machine, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 16/21] hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 08/21] aspeed/i2c: Handle receive command in separate function, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 11/21] hw/arm/smmuv3: fix eventq recording and IRQ triggerring, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 07/21] aspeed/i2c: interrupts should be cleared by software only, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 13/21] hw/intc/arm_gic: Drop GIC_BASE_IRQ macro, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 15/21] hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 12/21] hw/intc/arm_gic: Document QEMU interface, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 10/21] hw/arm/smmu-common: Fix the name of the iommu memory regions, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 09/21] aspeed/i2c: Fix receive done interrupt handling,
Peter Maydell <=
- [Qemu-devel] [PULL 17/21] aspeed/timer: fix compile breakage with clang 3.4.2, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 14/21] hw/net/pcnet-pci: Convert away from old_mmio accessors, Peter Maydell, 2018/09/25