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[Qemu-devel] [PULL 12/21] hw/intc/arm_gic: Document QEMU interface
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/21] hw/intc/arm_gic: Document QEMU interface |
Date: |
Tue, 25 Sep 2018 14:41:35 +0100 |
The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the header
file which documents it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
include/hw/intc/arm_gic.h | 43 +++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 42bb535fd45..ed703a17203 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -18,6 +18,49 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ * QEMU interface:
+ * + QOM property "num-cpu": number of CPUs to support
+ * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
+ * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
+ * + QOM property "has-security-extensions": set true if the GIC should
+ * implement the security extensions
+ * + QOM property "has-virtualization-extensions": set true if the GIC should
+ * implement the virtualization extensions
+ * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
+ * [0..P-1] SPIs
+ * [P..P+31] PPIs for CPU 0
+ * [P+32..P+63] PPIs for CPU 1
+ * ...
+ * + sysbus IRQs: (in order; number will vary depending on number of cores)
+ * - IRQ for CPU 0
+ * - IRQ for CPU 1
+ * ...
+ * - FIQ for CPU 0
+ * - FIQ for CPU 1
+ * ...
+ * - VIRQ for CPU 0 (exists even if virt extensions not present)
+ * - VIRQ for CPU 1 (exists even if virt extensions not present)
+ * ...
+ * - VFIQ for CPU 0 (exists even if virt extensions not present)
+ * - VFIQ for CPU 1 (exists even if virt extensions not present)
+ * ...
+ * - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
+ * - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
+ * + sysbus MMIO regions: (in order; numbers will vary depending on
+ * whether virtualization extensions are present and on number of cores)
+ * - distributor registers (GICD*)
+ * - CPU interface for the accessing core (GICC*)
+ * - virtual interface control registers (GICH*) (only if virt extns
present)
+ * - virtual CPU interface for the accessing core (GICV*) (only if virt)
+ * - CPU 0 CPU interface registers
+ * - CPU 1 CPU interface registers
+ * ...
+ * - CPU 0 virtual interface control registers (only if virt extns present)
+ * - CPU 1 virtual interface control registers (only if virt extns present)
+ * ...
+ */
+
#ifndef HW_ARM_GIC_H
#define HW_ARM_GIC_H
--
2.19.0
- [Qemu-devel] [PULL 05/21] arm: Add Nordic Semiconductor nRF51 SoC, (continued)
- [Qemu-devel] [PULL 05/21] arm: Add Nordic Semiconductor nRF51 SoC, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 19/21] hw/arm/aspeed: Add an Aspeed machine class, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 06/21] arm: Add BBC micro:bit machine, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 16/21] hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 08/21] aspeed/i2c: Handle receive command in separate function, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 11/21] hw/arm/smmuv3: fix eventq recording and IRQ triggerring, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 07/21] aspeed/i2c: interrupts should be cleared by software only, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 13/21] hw/intc/arm_gic: Drop GIC_BASE_IRQ macro, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 15/21] hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 12/21] hw/intc/arm_gic: Document QEMU interface,
Peter Maydell <=
- [Qemu-devel] [PULL 10/21] hw/arm/smmu-common: Fix the name of the iommu memory regions, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 09/21] aspeed/i2c: Fix receive done interrupt handling, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 17/21] aspeed/timer: fix compile breakage with clang 3.4.2, Peter Maydell, 2018/09/25
- [Qemu-devel] [PULL 14/21] hw/net/pcnet-pci: Convert away from old_mmio accessors, Peter Maydell, 2018/09/25