[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH v4 3/9] x86_iommu/amd: remove V=1 check from amd

From: Peter Xu
Subject: Re: [Qemu-devel] [PATCH v4 3/9] x86_iommu/amd: remove V=1 check from amdvi_validate_dte()
Date: Fri, 28 Sep 2018 13:46:38 +0800
User-agent: Mutt/1.10.1 (2018-07-13)

On Thu, Sep 27, 2018 at 04:45:55PM +0000, Singh, Brijesh wrote:
> Currently, the amdvi_validate_dte() assumes that a valid DTE will
> always have V=1. This is not true. The V=1 means that bit[127:1] are
> valid. A valid DTE can have IV=1 and V=0 (i.e address translation
> disabled and interrupt remapping enabled)
> Remove the V=1 check from amdvi_validate_dte(), make the caller
> responsible to check for V or IV bits.
> Signed-off-by: Brijesh Singh <address@hidden>
> Cc: Peter Xu <address@hidden>
> Cc: "Michael S. Tsirkin" <address@hidden>
> Cc: Paolo Bonzini <address@hidden>
> Cc: Richard Henderson <address@hidden>
> Cc: Eduardo Habkost <address@hidden>
> Cc: Marcel Apfelbaum <address@hidden>
> Cc: Tom Lendacky <address@hidden>
> Cc: Suravee Suthikulpanit <address@hidden>

Maybe also mentioning:

      This also fixes a bug in existing code that when error is
      detected during the translation we'll fail the translation
      instead of assuming a passthrough mode.

Not sure whether this can be done by maintainer.  Anyways:

Reviewed-by: Peter Xu <address@hidden>

Peter Xu

reply via email to

[Prev in Thread] Current Thread [Next in Thread]