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[Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override fl
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node |
Date: |
Fri, 18 Jan 2019 14:57:18 +0000 |
From: Eric Auger <address@hidden>
Let's report IO-coherent access is supported for translation
table walks, descriptor fetches and queues by setting the COHACC
override flag. Without that, we observe wrong command opcodes.
The DT description also advertises the dma coherency.
Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Eric Auger <address@hidden>
Reported-by: Shameerali Kolothum Thodi <address@hidden>
Tested-by: Shameer Kolothum <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/acpi/acpi-defs.h | 2 ++
hw/arm/virt-acpi-build.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 5021cb9e791..df37f687579 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -623,6 +623,8 @@ struct AcpiIortItsGroup {
} QEMU_PACKED;
typedef struct AcpiIortItsGroup AcpiIortItsGroup;
+#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
+
struct AcpiIortSmmu3 {
ACPI_IORT_NODE_HEADER_DEF
uint64_t base_address;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 95fad6f0ce2..04b62c714d9 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -418,6 +418,7 @@ build_iort(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
smmu->mapping_count = cpu_to_le32(1);
smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
+ smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
smmu->event_gsiv = cpu_to_le32(irq);
smmu->pri_gsiv = cpu_to_le32(irq + 1);
smmu->gerr_gsiv = cpu_to_le32(irq + 2);
--
2.20.1
- [Qemu-devel] [PULL 00/49] target-arm queue, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node,
Peter Maydell <=
- [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac), Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src, Peter Maydell, 2019/01/18