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[Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg |
Date: |
Fri, 18 Jan 2019 14:57:33 +0000 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e6017530326..fa50003f0b0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
{
unsigned int opc, op2, op3, rn, op4;
TCGv_i64 dst;
+ TCGv_i64 modifier;
opc = extract32(insn, 21, 4);
op2 = extract32(insn, 16, 5);
@@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s,
uint32_t insn)
case 2: /* RET */
switch (op3) {
case 0:
+ /* BR, BLR, RET */
if (op4 != 0) {
goto do_unallocated;
}
dst = cpu_reg(s, rn);
break;
+ case 2:
+ case 3:
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (opc == 2) {
+ /* RETAA, RETAB */
+ if (rn != 0x1f || op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ rn = 30;
+ modifier = cpu_X[31];
+ } else {
+ /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
+ if (op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ modifier = new_tmp_a64_zero(s);
+ }
+ if (s->pauth_active) {
+ dst = new_tmp_a64(s);
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+ }
+ } else {
+ dst = cpu_reg(s, rn);
+ }
+ break;
+
default:
goto do_unallocated;
}
@@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s,
uint32_t insn)
}
break;
+ case 8: /* BRAA */
+ case 9: /* BLRAA */
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (op3 != 2 || op3 != 3) {
+ goto do_unallocated;
+ }
+ if (s->pauth_active) {
+ dst = new_tmp_a64(s);
+ modifier = cpu_reg_sp(s, op4);
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+ }
+ } else {
+ dst = cpu_reg(s, rn);
+ }
+ gen_a64_set_pc(s, dst);
+ /* BLRAA also needs to load return address */
+ if (opc == 9) {
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+ }
+ break;
+
case 4: /* ERET */
if (s->current_el == 0) {
goto do_unallocated;
}
switch (op3) {
- case 0:
+ case 0: /* ERET */
if (op4 != 0) {
goto do_unallocated;
}
@@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
offsetof(CPUARMState, elr_el[s->current_el]));
break;
+ case 2: /* ERETAA */
+ case 3: /* ERETAB */
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (rn != 0x1f || op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ dst = tcg_temp_new_i64();
+ tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPUARMState, elr_el[s->current_el]));
+ if (s->pauth_active) {
+ modifier = cpu_X[31];
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, dst, modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, dst, modifier);
+ }
+ }
+ break;
+
default:
goto do_unallocated;
}
--
2.20.1
- [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC, (continued)
- [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac), Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg,
Peter Maydell <=
- [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space, Peter Maydell, 2019/01/18