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Re: [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to d
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree |
Date: |
Sun, 20 Jan 2019 08:51:04 +1100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
> +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
Not an issue with this patch set, since you are just moving existing code.
However, while I'm thinking about it:
It just occured to me that these uses of INT32_MIN are not ideal, in that they
are (signed) -0x80000000 and not 0x0000000080000000ull.
In particular, FNEG will remove the NaN-box of the 32-bit value.
Similarly with the construction of fsgnjn_s wrt not + deposit. It might be
better to simply xor the sign bit rather than not the whole 64-bit value.
Have you tried using RISU to compare these sorts of results vs real hardware,
or spike?
r~
- Re: [Qemu-devel] [PATCH v4 16/35] target/riscv: Convert RV priv insns to decodetree, (continued)
- [Qemu-devel] [PATCH v4 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/18
- Re: [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/18
- [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/18
[Qemu-devel] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/18
[Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/18