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[Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable |
Date: |
Tue, 16 Apr 2019 13:57:19 +0100 |
Enforce that for M-profile various FPSCR bits which are RES0 there
but have defined meanings on A-profile are never settable. This
ensures that M-profile code can't enable the A-profile behaviour
(notably vector length/stride handling) by accident.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/vfp_helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 2468fc16294..7a46d991486 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -105,6 +105,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
val &= ~FPCR_FZ16;
}
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ /*
+ * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
+ * and also for the trapped-exception-handling bits IxE.
+ */
+ val &= 0xf7c0009f;
+ }
+
/*
* We don't implement trapped exception handling, so the
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
--
2.20.1
- [Qemu-devel] [PATCH 00/26] target/arm: Implement M profile floating point, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable,
Peter Maydell <=
- [Qemu-devel] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 06/26] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present, Peter Maydell, 2019/04/16