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Re: [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW |
Date: |
Fri, 23 Aug 2019 07:45:04 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 8/23/19 6:04 AM, Peter Maydell wrote:
>> +static bool trans_ADR(DisasContext *s, arg_ri *a)
>> +{
>> + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm));
>> + return true;
>> +}
...
>> - if (rn == 13 && rd == 13) {
>> - /* ADD SP, SP, imm or SUB SP, SP, imm */
>> - store_sp_checked(s, tmp);
>> - } else {
>> - store_reg(s, rd, tmp);
>> - }
>> + /* Add/sub 12-bit immediate, in decodetree */
>> + goto illegal_op;
>
> We seem to have lost the store_sp_checked() handling ?
Not from ADR, which of course is ADD RD, PC, IMM, and so wouldn't match.
>> +&ri rd imm
>> &r rm
>> &i imm
>> &msr_reg rn r mask
>
> Should this change be in some other patch ?
No, it's used by ADR.
>> + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \
>> + &ri imm=%imm12_26_12_0
... here.
>> + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12
The rest of the store_sp_checked handling is here in the existing ADD path.
Recall STREG_SP_CHECK from patch 2.
r~
- [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, (continued)
[Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/08/19
[Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/08/19