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[PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
From: |
Peter Maydell |
Subject: |
[PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots |
Date: |
Fri, 27 Sep 2019 15:42:48 +0100 |
If we're booting a Linux kernel directly into Non-Secure
state on a CPU which has Secure state, then make sure we
set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
to access the FPU. Otherwise an AArch32 kernel will UNDEF as
soon as it tries to use the FPU.
It used to not matter that we didn't do this until commit
fc1120a7f5f2d4b6, where we implemented actually honouring
these NSACR bits.
The problem only exists for CPUs where EL3 is AArch32; the
equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
not trap, 1 to trap", so the reset value of the register
permits NS access, unlike NSACR.
Fixes: fc1120a7f5
Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/arm/boot.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index bf97ef3e339..25422660545 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque)
(cs != first_cpu || !info->secure_board_setup)) {
/* Linux expects non-secure state */
env->cp15.scr_el3 |= SCR_NS;
+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
+ env->cp15.nsacr |= 3 << 10;
}
}
--
2.20.1
- [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/27
- [PULL 2/9] tests/tcg: clean-up some comments after the de-tangling, Peter Maydell, 2019/09/27
- [PULL 3/9] target/arm: handle M-profile semihosting at translate time, Peter Maydell, 2019/09/27
- [PULL 4/9] target/arm: handle A-profile semihosting at translate time, Peter Maydell, 2019/09/27
- [PULL 9/9] hw/arm/boot: Use the IEC binary prefix definitions, Peter Maydell, 2019/09/27
- [PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs, Peter Maydell, 2019/09/27
- [PULL 7/9] tests/tcg: add linux-user semihosting smoke test for ARM, Peter Maydell, 2019/09/27
- [PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots,
Peter Maydell <=
- [PULL 5/9] target/arm: remove run time semihosting checks, Peter Maydell, 2019/09/27
- [PULL 6/9] target/arm: remove run-time semihosting checks for linux-user, Peter Maydell, 2019/09/27
- Re: [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/30