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[PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM
From: |
Peter Maydell |
Subject: |
[PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM |
Date: |
Fri, 14 Feb 2020 17:51:07 +0000 |
Now we have isar_feature test functions that look at fields in the
ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads
these register values from KVM so that the checks behave correctly
when we're using KVM.
No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we
add it to maintain the invariant that every field in the
ARMISARegisters struct is populated for a KVM CPU and can be relied
on. This requirement isn't actually written down yet, so add a note
to the relevant comment.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 5 +++++
target/arm/kvm32.c | 8 ++++++++
target/arm/kvm64.c | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3c996db3e45..e043932fcb1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -853,6 +853,11 @@ struct ARMCPU {
* prefix means a constant register.
* Some of these registers are split out into a substructure that
* is shared with the translators to control the ISA.
+ *
+ * Note that if you add an ID register to the ARMISARegisters struct
+ * you need to also update the 32-bit and 64-bit versions of the
+ * kvm_arm_get_host_cpu_features() function to correctly populate the
+ * field by reading the value from the KVM vCPU.
*/
struct ARMISARegisters {
uint32_t id_isar0;
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 3a8b437eef0..bca02553b25 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -97,6 +97,9 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->isar.id_isar6 = 0;
}
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
+ ARM_CP15_REG32(0, 0, 1, 2));
+
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
KVM_REG_ARM | KVM_REG_SIZE_U32 |
KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
@@ -108,6 +111,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
* Fortunately there is not yet anything in there that affects migration.
*/
+ /*
+ * There is no way to read DBGDIDR, because currently 32-bit KVM
+ * doesn't implement debug at all. Leave it at zero.
+ */
+
kvm_arm_destroy_scratch_host_vcpu(fdarray);
if (err < 0) {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 3bae9e4a663..527532f2b37 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -541,6 +541,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
} else {
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
ARM64_SYS_REG(3, 0, 0, 4, 1));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
+ ARM64_SYS_REG(3, 0, 0, 5, 0));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
+ ARM64_SYS_REG(3, 0, 0, 5, 1));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
ARM64_SYS_REG(3, 0, 0, 6, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
@@ -559,6 +563,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* than skipping the reads and leaving 0, as we must avoid
* considering the values in every case.
*/
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
+ ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
ARM64_SYS_REG(3, 0, 0, 2, 0));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
@@ -580,6 +586,36 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
+
+ /*
+ * DBGDIDR is a bit complicated because the kernel doesn't
+ * provide an accessor for it in 64-bit mode, which is what this
+ * scratch VM is in, and there's no architected "64-bit sysreg
+ * which reads the same as the 32-bit register" the way there is
+ * for other ID registers. Instead we synthesize a value from the
+ * AArch64 ID_AA64DFR0, the same way the kernel code in
+ * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
+ * We only do this if the CPU supports AArch32 at EL1.
+ */
+ if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
+ int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
+ int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
+ int ctx_cmps =
+ FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
+ int version = 6; /* ARMv8 debug architecture */
+ bool has_el3 =
+ !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
+ uint32_t dbgdidr = 0;
+
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
+ dbgdidr |= (1 << 16); /* RES1 bit */
+ ahcf->isar.dbgdidr = dbgdidr;
+ }
}
sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) >
0;
--
2.20.1
- [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function, (continued)
- [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/14
- [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/14
- [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/14
- [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/14
- [PATCH v2 05/21] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/14
- [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/14
- [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/14
- [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM,
Peter Maydell <=
- [PATCH v2 16/21] target/arm: Correct definition of PMCRDP, Peter Maydell, 2020/02/14
- [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/14
- [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/14
- [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature, Peter Maydell, 2020/02/14
- [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields, Peter Maydell, 2020/02/14
- [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/14