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Re: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KV
From: |
Richard Henderson |
Subject: |
Re: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM |
Date: |
Fri, 14 Feb 2020 12:27:07 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/14/20 9:51 AM, Peter Maydell wrote:
> + /*
> + * DBGDIDR is a bit complicated because the kernel doesn't
> + * provide an accessor for it in 64-bit mode, which is what this
> + * scratch VM is in, and there's no architected "64-bit sysreg
> + * which reads the same as the 32-bit register" the way there is
> + * for other ID registers. Instead we synthesize a value from the
> + * AArch64 ID_AA64DFR0, the same way the kernel code in
> + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
> + * We only do this if the CPU supports AArch32 at EL1.
> + */
> + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
> + int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
> + int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
> + int ctx_cmps =
> + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
> + int version = 6; /* ARMv8 debug architecture */
> + bool has_el3 =
> + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
> + uint32_t dbgdidr = 0;
> +
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
> + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
> + dbgdidr |= (1 << 16); /* RES1 bit */
I see the RES1 bit as 15.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, (continued)
- [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/14
- [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/14
- [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/14
- [PATCH v2 05/21] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/14
- [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/14
- [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/14
- [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/14
- Re: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM,
Richard Henderson <=
- [PATCH v2 16/21] target/arm: Correct definition of PMCRDP, Peter Maydell, 2020/02/14
- [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/14
- [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/14
- [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature, Peter Maydell, 2020/02/14
- [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields, Peter Maydell, 2020/02/14
- [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/14