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[PATCH v2 16/21] target/arm: Correct definition of PMCRDP
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From: |
Peter Maydell |
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Subject: |
[PATCH v2 16/21] target/arm: Correct definition of PMCRDP |
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Date: |
Fri, 14 Feb 2020 17:51:11 +0000 |
The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
Correct our #define of PMCRDP and add the missing PMCRX.
We do have the correct behaviour for handling the DP bit being
set, so this fixes a guest-visible bug.
Fixes: 033614c47de
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2feded1518c..2ebfa6c6545 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1017,7 +1017,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
#define PMCRN_MASK 0xf800
#define PMCRN_SHIFT 11
#define PMCRLC 0x40
-#define PMCRDP 0x10
+#define PMCRDP 0x20
+#define PMCRX 0x10
#define PMCRD 0x8
#define PMCRC 0x4
#define PMCRP 0x2
--
2.20.1
- Re: [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, (continued)
- [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/14
- [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/14
- [PATCH v2 05/21] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/14
- [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/14
- [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/14
- [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/14
- [PATCH v2 16/21] target/arm: Correct definition of PMCRDP,
Peter Maydell <=
- [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/14
- [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/14
- [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature, Peter Maydell, 2020/02/14
- [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields, Peter Maydell, 2020/02/14
- [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/14
- [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2, Peter Maydell, 2020/02/14