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[PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD I
From: |
Peter Maydell |
Subject: |
[PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS |
Date: |
Fri, 21 Feb 2020 13:06:57 +0000 |
From: Richard Henderson <address@hidden>
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b83d09dbcd7..bd68588a710 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int
rn,
write_vec_element(s, tmp, rd, dst_index, size);
tcg_temp_free_i64(tmp);
+
+ /* INS is considered a 128-bit write for SVE. */
+ clear_vec_high(s, true, rd);
}
@@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int
rn, int imm5)
idx = extract32(imm5, 1 + size, 4 - size);
write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
+
+ /* INS is considered a 128-bit write for SVE. */
+ clear_vec_high(s, true, rd);
}
/*
--
2.20.1
- [PULL 01/52] aspeed/scu: Create separate write callbacks, (continued)
- [PULL 01/52] aspeed/scu: Create separate write callbacks, Peter Maydell, 2020/02/21
- [PULL 02/52] aspeed/scu: Implement chip ID register, Peter Maydell, 2020/02/21
- [PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register, Peter Maydell, 2020/02/21
- [PULL 04/52] mainstone: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 05/52] z2: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT, Peter Maydell, 2020/02/21
- [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX, Peter Maydell, 2020/02/21
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth, Peter Maydell, 2020/02/21
- [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both, Peter Maydell, 2020/02/21
- [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Peter Maydell, 2020/02/21
- [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS,
Peter Maydell <=
- [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae, Peter Maydell, 2020/02/21
- [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/21
- [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid, Peter Maydell, 2020/02/21
- [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/21
- [PULL 17/52] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/21
- [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/21
- [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/21
- [PULL 18/52] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/21
- [PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/21
- [PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/21