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[PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop asserti
From: |
Alistair Francis |
Subject: |
[PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion |
Date: |
Mon, 13 Jul 2020 17:32:47 -0700 |
From: Frank Chang <frank.chang@sifive.com>
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index dc333e6a91..433cdacbe1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b)
static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
{
+ static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
static const GVecGen2s rsub_op[4] = {
{ .fni8 = gen_vec_rsub8_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs8,
+ .opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_vec_rsub16_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs16,
+ .opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_rsub_i32,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs32,
+ .opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = gen_rsub_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs64,
+ .opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
--
2.27.0
- [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware, Alistair Francis, 2020/07/13
- [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries, Alistair Francis, 2020/07/13
- [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM, Alistair Francis, 2020/07/13
- [PULL 03/15] riscv: Unify Qemu's reset vector code path, Alistair Francis, 2020/07/13
- [PULL 05/15] riscv: Add opensbi firmware dynamic support, Alistair Francis, 2020/07/13
- [PULL 06/15] RISC-V: Support 64 bit start address, Alistair Francis, 2020/07/13
- [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000, Alistair Francis, 2020/07/13
- [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion,
Alistair Francis <=
- [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), Alistair Francis, 2020/07/13
- [PULL 10/15] target/riscv: fix return value of do_opivx_widen(), Alistair Francis, 2020/07/13
- [PULL 11/15] target/riscv: fix vill bit index in vtype register, Alistair Francis, 2020/07/13
- [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model, Alistair Francis, 2020/07/13
- [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API, Alistair Francis, 2020/07/13
- [PULL 14/15] tcg/riscv: Remove superfluous breaks, Alistair Francis, 2020/07/13
- [PULL 15/15] target/riscv: Fix pmp NA4 implementation, Alistair Francis, 2020/07/13
- Re: [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- Re: [PULL 00/15] riscv-to-apply queue, Peter Maydell, 2020/07/14