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[PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_
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From: |
Alistair Francis |
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Subject: |
[PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() |
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Date: |
Mon, 13 Jul 2020 17:32:48 -0700 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a,
TCGv_i64 b)
static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- tcg_gen_vec_sub8_i64(d, b, a);
+ tcg_gen_vec_sub16_i64(d, b, a);
}
static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
--
2.27.0
- [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware, Alistair Francis, 2020/07/13
- [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries, Alistair Francis, 2020/07/13
- [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM, Alistair Francis, 2020/07/13
- [PULL 03/15] riscv: Unify Qemu's reset vector code path, Alistair Francis, 2020/07/13
- [PULL 05/15] riscv: Add opensbi firmware dynamic support, Alistair Francis, 2020/07/13
- [PULL 06/15] RISC-V: Support 64 bit start address, Alistair Francis, 2020/07/13
- [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000, Alistair Francis, 2020/07/13
- [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, Alistair Francis, 2020/07/13
- [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(),
Alistair Francis <=
- [PULL 10/15] target/riscv: fix return value of do_opivx_widen(), Alistair Francis, 2020/07/13
- [PULL 11/15] target/riscv: fix vill bit index in vtype register, Alistair Francis, 2020/07/13
- [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model, Alistair Francis, 2020/07/13
- [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API, Alistair Francis, 2020/07/13
- [PULL 14/15] tcg/riscv: Remove superfluous breaks, Alistair Francis, 2020/07/13
- [PULL 15/15] target/riscv: Fix pmp NA4 implementation, Alistair Francis, 2020/07/13
- Re: [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- Re: [PULL 00/15] riscv-to-apply queue, Peter Maydell, 2020/07/14