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Re: [PATCH-for-5.2] target/mips: Report unimplemented cache() operations

From: Philippe Mathieu-Daudé
Subject: Re: [PATCH-for-5.2] target/mips: Report unimplemented cache() operations
Date: Thu, 6 Aug 2020 23:37:46 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0

On 8/6/20 10:51 PM, Peter Maydell wrote:
> On Thu, 6 Aug 2020 at 21:31, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> On 8/6/20 8:01 PM, Jiaxun Yang wrote:
>>> 在 2020/8/6 下午8:26, Philippe Mathieu-Daudé 写道:
>>>> We only implement the Index[Store/Load]Tag from the 'cache' opcode.
>>>> Instead of ignoring the other cache operations, report them as
>>>> unimplemented.
>>> Hmm, I don't think we have anything to do with Invalidate/Writeback etc.
>>> opcodes
>>> in QEMU. Why do we log this?
>> I'm noticed this code is run on Linux 3.3.8 (4KEc):
>>     8880:       3082000f        andi    v0,a0,0xf
>>     8884:       10800008        beqz    a0,88a8
>>     8888:       00a21021        addu    v0,a1,v0
>>     888c:       08002227        j       889c
>>     8890:       00001821        move    v1,zero
>>     8894:       bcf90000        cache   0x19,0(a3)
>>     8898:       24630010        addiu   v1,v1,16
>>     889c:       0062302b        sltu    a2,v1,v0
>>     88a0:       14c0fffc        bnez    a2,8894
>>     88a4:       00833821        addu    a3,a0,v1
>>     88a8:       03e00008        jr      ra
>>     88ac:       00000000        nop
>> Why silently ignore the opcode is not implemented instead of logging it?
> I think the question is whether the opcode is supposed to have
> some behaviour which we're not implementing, or whether "no-op"
> is the correct behaviour for it (which it usually is for
> cache invalidate type operations; compare the way the Arm
> cache ops like IC_IALLU are just ARM_CP_NOP ops).

OK now I understand better, thanks.

I haven't found useful information about this 0x19=25 opcode value.

On a r10k core it is listed as 'Hit Writeback Invalidate (D)' but here
this is a 4kEc. The address used is a SRAM shared with a embedded DSP
on the same SoC. From a RevEng PoV it is helpful to see there is a such
cache access, as I can separate better the peripheral involved.
I'm happy using a trace event instead.

Jiaxun, can you list me the list of opcodes QEMU can safely ignore from
the TCG emulation PoV? That way we can comment them in the code such:

    switch (op) {
    case 9:
        /* Index Store Tag */
    case 5:
        /* Index Load Tag */
    case X:
    case Y:
    case Z:
        /* No-Op for QEMU */
        qemu_log_mask(LOG_UNIMP, "cache %u\n", op);



> thanks
> -- PMM

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