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Re: [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5)
From: |
Markus Armbruster |
Subject: |
Re: [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5) |
Date: |
Fri, 13 Nov 2020 08:47:59 +0100 |
User-agent: |
Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) |
Eric Blake <eblake@redhat.com> writes:
> On 11/10/20 11:47 PM, Ben Widawsky wrote:
>> A CXL memory device (AKA Type 3) is a CXL component that contains some
>> combination of volatile and persistent memory. It also implements the
>> previously defined mailbox interface as well as the memory device
>> firmware interface.
>>
>> The following example will create a 256M device in a 512M window:
>>
>> -object "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M"
>> -device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M"
>>
>> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
>> ---
>
>> +++ b/qapi/machine.json
>> @@ -1394,6 +1394,7 @@
>> { 'union': 'MemoryDeviceInfo',
>> 'data': { 'dimm': 'PCDIMMDeviceInfo',
>> 'nvdimm': 'PCDIMMDeviceInfo',
>> + 'cxl': 'PCDIMMDeviceInfo',
>> 'virtio-pmem': 'VirtioPMEMDeviceInfo',
>> 'virtio-mem': 'VirtioMEMDeviceInfo'
>> }
>
> Missing documentation of the new data type, and the fact that it will be
> introduced in 6.0.
Old wish list item: improve the QAPI schema frontend to flag this.
> Also, Markus has been trying to get rid of so-called
> "simple unions" in favor of "flat unions" - every time we modify an
> existing simple union, it is worth asking if it is time to first flatten
> this.
0. Simple unions can be transformed into flat unions. The
transformation can either preserve the nested wire format, or flatten
it. See docs/devel/qapi-code-gen.txt "A simple union can always be
re-written as a flat union ..."
1. No new simple unions.
2. Existing simple unions that can be flattened without breaking
backward compatibility have long been flattened.
3. The remaining simple unions are part of QMP, where we need to
preserve the wire format. We could turn them into flat union preserving
the wire format. Only worthwhile if we kill simple unions and simplify
scripts/qapi/. Opportunity to make the flat union syntax less
cumbersome. Not done due to lack of time.
4. Kevin and I have been experimenting with ways to provide both flat
and nested wire format. This would pave the way for orderly deprecation
of the nested wire format. May not be practical for QMP output.
- [RFC PATCH 13/25] hw/pci: Plumb _UID through host bridges, (continued)
- [RFC PATCH 13/25] hw/pci: Plumb _UID through host bridges, Ben Widawsky, 2020/11/11
- [RFC PATCH 14/25] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Ben Widawsky, 2020/11/11
- [RFC PATCH 15/25] acpi/pxb/cxl: Reserve host bridge MMIO, Ben Widawsky, 2020/11/11
- [RFC PATCH 16/25] hw/pxb/cxl: Add "windows" for host bridges, Ben Widawsky, 2020/11/11
- [RFC PATCH 17/25] hw/cxl/rp: Add a root port, Ben Widawsky, 2020/11/11
- [RFC PATCH 18/25] hw/cxl/device: Add a memory device (8.2.8.5), Ben Widawsky, 2020/11/11
[RFC PATCH 19/25] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Ben Widawsky, 2020/11/11
[RFC PATCH 20/25] acpi/cxl: Add _OSC implementation (9.14.2), Ben Widawsky, 2020/11/11
[RFC PATCH 22/25] acpi/cxl: Create the CEDT (9.14.1), Ben Widawsky, 2020/11/11
[RFC PATCH 21/25] acpi/cxl: Introduce a compat-driver UUID for CXL _OSC, Ben Widawsky, 2020/11/11
[RFC PATCH 23/25] Temp: acpi/cxl: Add ACPI0017 (CEDT awareness), Ben Widawsky, 2020/11/11