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[PULL 16/19] hw/ppc: e500: Use a macro for the platform clock frequency
From: |
David Gibson |
Subject: |
[PULL 16/19] hw/ppc: e500: Use a macro for the platform clock frequency |
Date: |
Wed, 10 Feb 2021 17:17:32 +1100 |
From: Bin Meng <bin.meng@windriver.com>
At present the platform clock frequency is using a magic number.
Convert it to a macro and use it everywhere.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1612362288-22216-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/e500.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index c64b5d08bd..c795276668 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -74,6 +74,8 @@
#define MPC8544_I2C_IRQ 43
#define RTC_REGS_OFFSET 0x68
+#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
+
struct boot_info
{
uint32_t dt_base;
@@ -320,8 +322,8 @@ static int ppce500_load_device_tree(PPCE500MachineState
*pms,
int fdt_size;
void *fdt;
uint8_t hypercall[16];
- uint32_t clock_freq = 400000000;
- uint32_t tb_freq = 400000000;
+ uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
+ uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
int i;
char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
char *soc;
@@ -890,7 +892,7 @@ void ppce500_init(MachineState *machine)
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
- ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
+ ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
/* Register reset handler */
if (!i) {
--
2.29.2
- [PULL 06/19] ppc/xive: Add firmware bit when dumping the ENDs, (continued)
- [PULL 06/19] ppc/xive: Add firmware bit when dumping the ENDs, David Gibson, 2021/02/10
- [PULL 08/19] ppc/pnv: Simplify pnv_bmc_create(), David Gibson, 2021/02/10
- [PULL 05/19] ppc/pnv: Add trace events for PCI event notification, David Gibson, 2021/02/10
- [PULL 09/19] ppc/pnv: Discard internal BMC initialization when BMC is external, David Gibson, 2021/02/10
- [PULL 03/19] spapr: Adjust firmware path of PCI devices, David Gibson, 2021/02/10
- [PULL 14/19] spapr_numa.c: fix ibm, max-associativity-domains calculation, David Gibson, 2021/02/10
- [PULL 19/19] target/ppc: Add E500 L2CSR0 write helper, David Gibson, 2021/02/10
- [PULL 07/19] ppc/pnv: Use skiboot addresses to load kernel and ramfs, David Gibson, 2021/02/10
- [PULL 10/19] ppc/pnv: Remove default disablement of the PNOR contents, David Gibson, 2021/02/10
- [PULL 11/19] ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR, David Gibson, 2021/02/10
- [PULL 16/19] hw/ppc: e500: Use a macro for the platform clock frequency,
David Gibson <=
- [PULL 12/19] spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c, David Gibson, 2021/02/10
- [PULL 18/19] hw/net: fsl_etsec: Reverse the RCTRL.RSF logic, David Gibson, 2021/02/10
- [PULL 13/19] spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper, David Gibson, 2021/02/10
- [PULL 15/19] ppc/pnv: Set default RAM size to 1 GB, David Gibson, 2021/02/10
- [PULL 17/19] hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes, David Gibson, 2021/02/10
- Re: [PULL 00/19] ppc-for-6.0 queue 20210210, Peter Maydell, 2021/02/10