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[PATCH v7 59/75] target/riscv: introduce floating-point rounding mode en
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From: |
frank . chang |
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Subject: |
[PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum |
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Date: |
Fri, 26 Feb 2021 11:18:43 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 7c4ab92ecbe..ad84aeebc1c 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == RISCV_FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case RISCV_FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case RISCV_FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case RISCV_FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case RISCV_FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case RISCV_FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index de7152dc323..3f453ed457a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2321,7 +2321,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2400,7 +2400,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2432,7 +2432,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2468,7 +2468,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2534,7 +2534,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2611,7 +2611,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2757,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2804,7 +2804,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 959b81b3016..469cc418c4e 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1);
extern const VMStateDescription vmstate_riscv_cpu;
#endif
+enum {
+ RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ RISCV_FRM_RTZ = 1, /* Round towards Zero */
+ RISCV_FRM_RDN = 2, /* Round Down */
+ RISCV_FRM_RUP = 3, /* Round Up */
+ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
- [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions, (continued)
- [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/02/25
- [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/02/25
- [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/02/25
- [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/02/25
- [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/02/25
- [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/02/25
- [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/02/25
- [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/02/25
- [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/02/25
- [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/02/25
- [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum,
frank . chang <=
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/02/25
- [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/02/25
- [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/02/25
- [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/02/25
- [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/02/25
- [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/02/25
- [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/02/25
- [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/02/25