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[PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exce
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From: |
frank . chang |
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Subject: |
[PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid |
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Date: |
Fri, 26 Feb 2021 11:18:50 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 03245f67c4b..2a3a437168f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2605,6 +2605,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
int rm)
{
if (checkfn(s, a)) {
+ if (rm != RISCV_FRM_DYN) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+ }
+
uint32_t data = 0;
TCGLabel *over = gen_new_label();
gen_set_rm(s, rm);
@@ -2690,6 +2694,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
TCGv_i64 t1;
if (s->vl_eq_vlmax) {
@@ -2772,6 +2778,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_widen_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2857,6 +2867,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr
*a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2897,6 +2911,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr
*a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opxfv_narrow_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##HELPER##_b, \
@@ -3372,6 +3390,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s
*a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
unsigned int ofs = (8 << s->sew);
unsigned int len = 64 - ofs;
TCGv_i64 t_nan;
@@ -3397,6 +3417,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f
*a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
/* The instructions ignore LMUL and vector register group. */
TCGv_i64 t1;
TCGLabel *over = gen_new_label();
--
2.17.1
- [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, (continued)
- [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/02/25
- [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/02/25
- [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/02/25
- [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/02/25
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/02/25
- [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/02/25
- [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/02/25
- [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/02/25
- [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid,
frank . chang <=
- [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/02/25
- [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/02/25
- [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/02/25
- [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/02/25
- [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/02/25
- [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/02/25
- [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/02/25