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[PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
From: |
frank . chang |
Subject: |
[PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits |
Date: |
Fri, 26 Feb 2021 11:18:48 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
--
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 367b182735f..ad2497229db 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,7 +103,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
-#define RV_VLEN_MAX 256
+#define RV_VLEN_MAX 1024
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f5c48db0e6..1f6cd7f97c6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -613,8 +613,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
base = tcg_temp_new();
/*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
+ * As simd_desc supports at most 2048 bytes, and in this implementation,
+ * the max vector group length is 4096 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8d389af4b78..16331939b64 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -129,7 +129,7 @@ static uint32_t vext_wd(uint32_t desc)
static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
/*
- * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
* so vlen in bytes (vlenb) is encoded as maxsz.
*/
uint32_t vlenb = simd_maxsz(desc);
--
2.17.1
- [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions, (continued)
- [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/02/25
- [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/02/25
- [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/02/25
- [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/02/25
- [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/02/25
- [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/02/25
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/02/25
- [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/02/25
- [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits,
frank . chang <=
- [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/02/25
- [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/02/25
- [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/02/25
- [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/02/25
- [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/02/25
- [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/02/25
- [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/02/25
- [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/02/25