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Re: [PATCH v2 10/24] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 f

From: Richard Henderson
Subject: Re: [PATCH v2 10/24] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
Date: Sun, 28 Feb 2021 19:38:50 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1

On 2/15/21 3:51 AM, Peter Maydell wrote:
The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.

Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible semantics via individual device properties, we make the
behaviour conditional on the part-number field of the SCC_ID register
which the board code already passes us.

For the AN524, the differences are:
  * CFG3 is reserved rather than being board switches
  * CFG5 is a new register ("ACLK Frequency in Hz")
  * CFG6 is a new register ("Clock divider for BRAM")

We implement both of the new registers as reads-as-written.

Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
  include/hw/misc/mps2-scc.h |  3 ++
  hw/misc/mps2-scc.c         | 71 ++++++++++++++++++++++++++++++++++++--
  2 files changed, 72 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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