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[RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Par
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) |
Date: |
Tue, 9 Mar 2021 15:56:43 +0100 |
Introduce the 'Parallel Extend Lower' opcodes:
- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Uses gen_pextw, still unoptimized, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg782796.html
---
target/mips/tx79.decode | 3 ++
target/mips/tx79_translate.c | 75 ++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index ead5f8281e5..98f21d33e3f 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -34,6 +34,9 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs
PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
+PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
+PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
+PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
# MMI1
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 68c56affc4c..c4656a4c21d 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -297,6 +297,81 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64
a, TCGv_i64 b)
tcg_gen_deposit_i64(dh, a, b, 0, 32);
}
+static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+{
+ TCGv_i64 ax, bx;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+ bx = tcg_temp_new_i64();
+
+ gen_load_gpr(ax, a->rs);
+ gen_load_gpr(bx, a->rt);
+
+ /* Lower half */
+ for (int i = 0; i < 64 / (2 * wlen); i++) {
+ tcg_gen_deposit_i64(cpu_gpr[a->rd],
+ cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
+ tcg_gen_deposit_i64(cpu_gpr[a->rd],
+ cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
+ tcg_gen_shri_i64(bx, bx, wlen);
+ tcg_gen_shri_i64(ax, ax, wlen);
+ }
+ /* Upper half */
+ for (int i = 0; i < 64 / (2 * wlen); i++) {
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+ cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+ cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
+ tcg_gen_shri_i64(bx, bx, wlen);
+ tcg_gen_shri_i64(ax, ax, wlen);
+ }
+
+ tcg_temp_free(bx);
+ tcg_temp_free(ax);
+
+ return true;
+}
+
+/* Parallel Extend Lower from Byte */
+static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_PEXTLx(ctx, a, 8);
+}
+
+/* Parallel Extend Lower from Halfword */
+static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_PEXTLx(ctx, a, 16);
+}
+
+/* Parallel Extend Lower from Word */
+static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
+{
+ TCGv_i64 ax, bx;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+ bx = tcg_temp_new_i64();
+
+ gen_load_gpr(ax, a->rs);
+ gen_load_gpr(bx, a->rt);
+ gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
+
+ tcg_temp_free(bx);
+ tcg_temp_free(ax);
+
+ return true;
+}
+
/* Parallel Extend Upper from Word */
static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
{
--
2.26.2
- [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64(), (continued)
- [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 05/22] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 06/22] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 07/22] target/mips: Remove 'C790 Multimedia Instructions' dead code, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 08/22] target/mips/tx79: Salvage instructions description comment, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 09/22] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower),
Philippe Mathieu-Daudé <=
- [RFC PATCH v2 13/22] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 14/22] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 15/22] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 16/22] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 17/22] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even), Philippe Mathieu-Daudé, 2021/03/09