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[RFC PATCH v2 16/22] target/mips/tx79: Introduce PINTEH (Parallel Interl
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 16/22] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) |
Date: |
Tue, 9 Mar 2021 15:56:47 +0100 |
Introduce the PINTEH opcode (Parallel Interleave Even Halfword).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
Use trans_parallel_arith (rth)
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 653910371d2..fbd2be569ad 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -57,6 +57,7 @@ PXOR 011100 ..... ..... ..... 10011 001001
@rs_rt_rd
# MMI3
+PINTEH 011100 ..... ..... ..... 01010 101001 @rs_rt_rd
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 90c33d26a9f..7c7879face0 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -593,3 +593,25 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
return true;
}
+
+static void gen_vec_pinteh(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 x, y, mask = tcg_constant_i64(0x0000ffff0000ffffull);
+
+ x = tcg_temp_new_i64();
+ y = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(x, a, 8);
+ tcg_gen_and_i64(x, x, mask);
+ tcg_gen_and_i64(y, b, mask);
+ tcg_gen_or_i64(d, x, y);
+
+ tcg_temp_free(y);
+ tcg_temp_free(x);
+}
+
+/* Parallel Interleave Even Halfword */
+static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_parallel_arith(ctx, a, gen_vec_pinteh);
+}
--
2.26.2
- Re: [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), (continued)
- [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 13/22] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 14/22] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 15/22] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 16/22] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword),
Philippe Mathieu-Daudé <=
- [RFC PATCH v2 17/22] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 18/22] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 19/22] target/mips/tx79: Introduce LQ opcode (Load Quadword), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 20/22] target/mips/tx79: Introduce SQ opcode (Store Quadword), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 21/22] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ(), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 22/22] target/mips: Reintroduce the R5900 CPU, Philippe Mathieu-Daudé, 2021/03/09
- Re: [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing), Philippe Mathieu-Daudé, 2021/03/11