[RFC PATCH v2 17/22] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)

[Philippe Mathieu-Daudé]

Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW
(Parallel Exchange Even Word) opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: unoptimized, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg782831.html
---
 target/mips/tx79.decode      |  2 ++
 target/mips/tx79_translate.c | 70 ++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index fbd2be569ad..0ea9fc95568 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -54,6 +54,8 @@ PEXTUW          011100 ..... ..... ..... 10010 101000   
@rs_rt_rd
 PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
 PAND            011100 ..... ..... ..... 10010 001001   @rs_rt_rd
 PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
+PEXEH           011100 00000 ..... ..... 11010 001001   @rt_rd
+PEXEW           011100 00000 ..... ..... 11110 001001   @rt_rd
 
 # MMI3
 
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 7c7879face0..b23e0a1b048 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -615,3 +615,73 @@ static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
 {
     return trans_parallel_arith(ctx, a, gen_vec_pinteh);
 }
+
+/* Parallel Exchange Even Halfword */
+static bool trans_PEXEH(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+
+    /* Lower half */
+    tcg_gen_mov_i64(ax, cpu_gpr[a->rt]);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
+    }
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 32, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 0, 16);
+
+    /* Upper half */
+    tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
+    }
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 32, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 0, 16);
+
+    tcg_temp_free(ax);
+
+    return true;
+}
+
+/* Parallel Exchange Even Word */
+static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ah, al;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ah = tcg_temp_new_i64();
+    al = tcg_temp_new_i64();
+
+    gen_load_gpr(ah, a->rt);
+    gen_load_gpr_hi(al, a->rt);
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], ah, al, 0, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], al, ah, 0, 32);
+
+    tcg_temp_free(al);
+    tcg_temp_free(ah);
+
+    return true;
+}
-- 
2.26.2