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[PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp
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From: |
Alistair Francis |
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Subject: |
[PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp |
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Date: |
Tue, 8 Jun 2021 10:29:28 +1000 |
From: Changbin Du <changbin.du@gmail.com>
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aa48bca830..ee2523f66b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
}
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
#endif
for (i = 0; i < 32; i++) {
--
2.31.1
- [PULL 03/32] hw/riscv: Support the official CLINT DT bindings, (continued)
- [PULL 03/32] hw/riscv: Support the official CLINT DT bindings, Alistair Francis, 2021/06/07
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings, Alistair Francis, 2021/06/07
- [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices, Alistair Francis, 2021/06/07
- [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage, Alistair Francis, 2021/06/07
- [PULL 07/32] hw/riscv: Use macros for BIOS image names, Alistair Francis, 2021/06/07
- [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot, Alistair Francis, 2021/06/07
- [PULL 09/32] target/riscv: fix wfi exception behavior, Alistair Francis, 2021/06/07
- [PULL 10/32] docs/system: Move the RISC-V -bios information to removed, Alistair Francis, 2021/06/07
- [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation, Alistair Francis, 2021/06/07
- [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration, Alistair Francis, 2021/06/07
- [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp,
Alistair Francis <=
- [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations, Alistair Francis, 2021/06/07
- [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz., Alistair Francis, 2021/06/07
- [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension, Alistair Francis, 2021/06/07
- [PULL 17/32] target/riscv: rvb: count leading/trailing zeros, Alistair Francis, 2021/06/07
- [PULL 18/32] target/riscv: rvb: count bits set, Alistair Francis, 2021/06/07
- [PULL 19/32] target/riscv: rvb: logic-with-negate, Alistair Francis, 2021/06/07
- [PULL 20/32] target/riscv: rvb: pack two words into one register, Alistair Francis, 2021/06/07
- [PULL 21/32] target/riscv: rvb: min/max instructions, Alistair Francis, 2021/06/07
- [PULL 22/32] target/riscv: rvb: sign-extend instructions, Alistair Francis, 2021/06/07
- [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, Alistair Francis, 2021/06/07