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[PULL 14/32] target/riscv/pmp: Add assert for ePMP operations
From: |
Alistair Francis |
Subject: |
[PULL 14/32] target/riscv/pmp: Add assert for ePMP operations |
Date: |
Tue, 8 Jun 2021 10:29:29 +1000 |
Although we construct epmp_operation in such a way that it can only be
between 0 and 15 Coverity complains that we don't handle the other
possible cases. To fix Coverity and make it easier for humans to read
add a default case to the switch statement that calls
g_assert_not_reached().
Fixes: CID 1453108
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id:
ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
---
target/riscv/pmp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 78203291de..82ed020b10 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -402,6 +402,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
case 15:
*allowed_privs = PMP_READ;
break;
+ default:
+ g_assert_not_reached();
}
} else {
switch (epmp_operation) {
@@ -433,6 +435,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
case 7:
*allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
break;
+ default:
+ g_assert_not_reached();
}
}
}
--
2.31.1
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings, (continued)
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings, Alistair Francis, 2021/06/07
- [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices, Alistair Francis, 2021/06/07
- [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage, Alistair Francis, 2021/06/07
- [PULL 07/32] hw/riscv: Use macros for BIOS image names, Alistair Francis, 2021/06/07
- [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot, Alistair Francis, 2021/06/07
- [PULL 09/32] target/riscv: fix wfi exception behavior, Alistair Francis, 2021/06/07
- [PULL 10/32] docs/system: Move the RISC-V -bios information to removed, Alistair Francis, 2021/06/07
- [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation, Alistair Francis, 2021/06/07
- [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration, Alistair Francis, 2021/06/07
- [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp, Alistair Francis, 2021/06/07
- [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations,
Alistair Francis <=
- [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz., Alistair Francis, 2021/06/07
- [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension, Alistair Francis, 2021/06/07
- [PULL 17/32] target/riscv: rvb: count leading/trailing zeros, Alistair Francis, 2021/06/07
- [PULL 18/32] target/riscv: rvb: count bits set, Alistair Francis, 2021/06/07
- [PULL 19/32] target/riscv: rvb: logic-with-negate, Alistair Francis, 2021/06/07
- [PULL 20/32] target/riscv: rvb: pack two words into one register, Alistair Francis, 2021/06/07
- [PULL 21/32] target/riscv: rvb: min/max instructions, Alistair Francis, 2021/06/07
- [PULL 22/32] target/riscv: rvb: sign-extend instructions, Alistair Francis, 2021/06/07
- [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, Alistair Francis, 2021/06/07
- [PULL 24/32] target/riscv: rvb: single-bit instructions, Alistair Francis, 2021/06/07