[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 0/7] riscv-to-apply queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 0/7] riscv-to-apply queue |
Date: |
Fri, 25 Jun 2021 18:55:20 +0100 |
On Thu, 24 Jun 2021 at 13:02, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:
>
> Merge remote-tracking branch
> 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24
> 09:31:26 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2
>
> for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:
>
> hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24
> 05:00:13 -0700)
>
> ----------------------------------------------------------------
> Third RISC-V PR for 6.1 release
>
> - Fix MISA in the DisasContext
> - Fix GDB CSR XML generation
> - QOMify the SiFive UART
> - Add support for the OpenTitan timer
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
- [PULL 0/7] riscv-to-apply queue, Alistair Francis, 2021/06/24
- [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer, Alistair Francis, 2021/06/24
- [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa, Alistair Francis, 2021/06/24
- [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation, Alistair Francis, 2021/06/24
- [PULL 3/7] hw/char: Consistent function names for sifive_uart, Alistair Francis, 2021/06/24
- [PULL 4/7] hw/char: QOMify sifive_uart, Alistair Francis, 2021/06/24
- [PULL 5/7] hw/char/ibex_uart: Make the register layout private, Alistair Francis, 2021/06/24
- [PULL 6/7] hw/timer: Initial commit of Ibex Timer, Alistair Francis, 2021/06/24
- Re: [PULL 0/7] riscv-to-apply queue,
Peter Maydell <=