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[PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in ic
From: |
Peter Maydell |
Subject: |
[PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write |
Date: |
Fri, 9 Jul 2021 17:09:51 +0100 |
From: Ricardo Koller <ricarkol@google.com>
icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs). The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1). The consequence is that
if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
guest is unable to deactivate the resulting IRQ. Note that other
functions that deal with large IRQ numbers, like icv_iar_read, check
against 1020 and not against num_irq.
Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
implemented IRQs.
Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-id: 20210702233701.3369-1-ricarkol@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 3e0641aff97..a032d505f53 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1227,7 +1227,7 @@ static void icv_dir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
- if (irq >= cs->gic->num_irq) {
+ if (irq >= GICV3_MAXIRQ) {
/* Also catches special interrupt numbers and LPIs */
return;
}
@@ -1262,7 +1262,7 @@ static void icv_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), value);
- if (irq >= cs->gic->num_irq) {
+ if (irq >= GICV3_MAXIRQ) {
/* Also catches special interrupt numbers and LPIs */
return;
}
--
2.20.1
- [PULL 00/17] target-arm queue, Peter Maydell, 2021/07/09
- [PULL 01/17] stm32f100: Add the stm32f100 SoC, Peter Maydell, 2021/07/09
- [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine, Peter Maydell, 2021/07/09
- [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write,
Peter Maydell <=
- [PULL 03/17] docs/system: arm: Add stm32 boards description, Peter Maydell, 2021/07/09
- [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase, Peter Maydell, 2021/07/09
- [PULL 09/17] hw/gpio/pl061: Document the interface of this device, Peter Maydell, 2021/07/09
- [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic, Peter Maydell, 2021/07/09
- [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints, Peter Maydell, 2021/07/09
- [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write, Peter Maydell, 2021/07/09
- [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset, Peter Maydell, 2021/07/09
- [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect, Peter Maydell, 2021/07/09
- [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message, Peter Maydell, 2021/07/09
- [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers, Peter Maydell, 2021/07/09