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[PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
From: |
Peter Maydell |
Subject: |
[PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase |
Date: |
Fri, 9 Jul 2021 17:09:50 +0100 |
From: Alexandre Iooss <erdnaxe@crans.org>
New mini-kernel test for STM32VLDISCOVERY USART1.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index d40adddafa3..96849cec915 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = {
0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
};
+static const uint8_t kernel_stm32vldiscovery[] = {
+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */
+ 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */
+ 0x00, 0x00, 0x00, 0x00, /* NMI */
+ 0x00, 0x00, 0x00, 0x00, /* Hard fault */
+ 0x00, 0x00, 0x00, 0x00, /* Memory management fault */
+ 0x00, 0x00, 0x00, 0x00, /* Bus fault */
+ 0x00, 0x00, 0x00, 0x00, /* Usage fault */
+ 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */
+ 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */
+ 0x1a, 0x68, /* ldr r2, [r3] */
+ 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x1a, 0x68, /* ldr r2, [r3] */
+ 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */
+ 0x45, 0x22, /* movs r2, #69 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */
+ 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */
+ 0x54, 0x22, /* movs r2, 'T' */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0xfe, 0xe7, /* b . */
+ 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */
+ 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */
+ 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */
+ 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */
+ 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */
+};
+
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@@ -144,6 +179,8 @@ static testdef_t tests[] = {
{ "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
{ "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+ { "arm", "stm32vldiscovery", "", "T",
+ sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
{ NULL }
};
--
2.20.1
- [PULL 00/17] target-arm queue, Peter Maydell, 2021/07/09
- [PULL 01/17] stm32f100: Add the stm32f100 SoC, Peter Maydell, 2021/07/09
- [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine, Peter Maydell, 2021/07/09
- [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write, Peter Maydell, 2021/07/09
- [PULL 03/17] docs/system: arm: Add stm32 boards description, Peter Maydell, 2021/07/09
- [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase,
Peter Maydell <=
- [PULL 09/17] hw/gpio/pl061: Document the interface of this device, Peter Maydell, 2021/07/09
- [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic, Peter Maydell, 2021/07/09
- [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints, Peter Maydell, 2021/07/09
- [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write, Peter Maydell, 2021/07/09
- [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset, Peter Maydell, 2021/07/09
- [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect, Peter Maydell, 2021/07/09
- [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message, Peter Maydell, 2021/07/09
- [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers, Peter Maydell, 2021/07/09
- [PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint, Peter Maydell, 2021/07/09
- [PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable, Peter Maydell, 2021/07/09