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[PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtrac
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) |
Date: |
Sun, 11 Jul 2021 23:00:01 +0200 |
Introduce the 'Parallel Subtract' opcodes:
- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel Subtract Word)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
---
target/mips/tcg/tx79.decode | 6 ++++++
target/mips/tcg/tx79_translate.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 26c80b9bce5..d1c07c7d901 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -29,6 +29,12 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
+# MMI0
+
+PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
+PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
+PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
+
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 00364f10d47..3abd1d92e70 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
#include "translate.h"
@@ -144,6 +145,24 @@ static bool trans_parallel_arith(DisasContext *ctx,
arg_rtype *a,
return true;
}
+/* Parallel Subtract Byte */
+static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64);
+}
+
+/* Parallel Subtract Halfword */
+static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64);
+}
+
+/* Parallel Subtract Word */
+static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64);
+}
+
/*
* Min/Max (4 instructions)
* ------------------------
--
2.31.1
- [PULL 00/19] MIPS patches for 2021-07-11, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 01/19] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract),
Philippe Mathieu-Daudé <=
- [PULL 02/19] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 05/19] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 07/19] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 08/19] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 09/19] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 10/19] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 13/19] target/mips: Rewrite UHI errno_mips() using switch statement, Philippe Mathieu-Daudé, 2021/07/11