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[PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword)
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword) |
Date: |
Sun, 11 Jul 2021 23:00:09 +0200 |
Introduce the SQ opcode (Store Quadword).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-27-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/tx79.decode | 1 +
target/mips/tcg/tx79_translate.c | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 0af5c6d0ed1..03a25a5096d 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -70,3 +70,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
# SPECIAL
LQ 011110 ..... ..... ................ @ldst
+SQ 011111 ..... ..... ................ @ldst
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index d9193b4d86e..395d6afa1f1 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -369,6 +369,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
return true;
}
+static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv addr = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, addr, a->base, a->offset);
+ /*
+ * Clear least-significant four bits of the effective
+ * address, effectively creating an aligned address.
+ */
+ tcg_gen_andi_tl(addr, addr, ~0xf);
+
+ /* Lower half */
+ gen_load_gpr(t0, a->rt);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+
+ /* Upper half */
+ tcg_gen_addi_i64(addr, addr, 8);
+ gen_load_gpr_hi(t0, a->rt);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(addr);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
--
2.31.1
- [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), (continued)
- [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 02/19] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 05/19] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 07/19] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 08/19] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 09/19] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 10/19] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword),
Philippe Mathieu-Daudé <=
- [PULL 13/19] target/mips: Rewrite UHI errno_mips() using switch statement, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 14/19] dp8393x: fix CAM descriptor entry index, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 15/19] dp8393x: Replace address_space_rw(is_write=1) by address_space_write(), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 16/19] dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 17/19] dp8393x: Store CAM registers as 16-bit, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 18/19] dp8393x: Rewrite dp8393x_get() / dp8393x_put(), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 19/19] dp8393x: don't force 32-bit register access, Philippe Mathieu-Daudé, 2021/07/11
- Re: [PULL 00/19] MIPS patches for 2021-07-11, Philippe Mathieu-Daudé, 2021/07/11