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[PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Ex
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) |
Date: |
Sun, 11 Jul 2021 23:00:03 +0200 |
Introduce the 'Parallel Extend Lower' opcodes:
- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-13-f4bug@amsat.org>
---
target/mips/tcg/tx79.decode | 3 ++
target/mips/tcg/tx79_translate.c | 75 ++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index ead5f8281e5..98f21d33e3f 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -34,6 +34,9 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs
PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
+PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
+PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
+PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
# MMI1
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 68c56affc4c..c4656a4c21d 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -297,6 +297,81 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64
a, TCGv_i64 b)
tcg_gen_deposit_i64(dh, a, b, 0, 32);
}
+static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+{
+ TCGv_i64 ax, bx;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+ bx = tcg_temp_new_i64();
+
+ gen_load_gpr(ax, a->rs);
+ gen_load_gpr(bx, a->rt);
+
+ /* Lower half */
+ for (int i = 0; i < 64 / (2 * wlen); i++) {
+ tcg_gen_deposit_i64(cpu_gpr[a->rd],
+ cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
+ tcg_gen_deposit_i64(cpu_gpr[a->rd],
+ cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
+ tcg_gen_shri_i64(bx, bx, wlen);
+ tcg_gen_shri_i64(ax, ax, wlen);
+ }
+ /* Upper half */
+ for (int i = 0; i < 64 / (2 * wlen); i++) {
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+ cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+ cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
+ tcg_gen_shri_i64(bx, bx, wlen);
+ tcg_gen_shri_i64(ax, ax, wlen);
+ }
+
+ tcg_temp_free(bx);
+ tcg_temp_free(ax);
+
+ return true;
+}
+
+/* Parallel Extend Lower from Byte */
+static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_PEXTLx(ctx, a, 8);
+}
+
+/* Parallel Extend Lower from Halfword */
+static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
+{
+ return trans_PEXTLx(ctx, a, 16);
+}
+
+/* Parallel Extend Lower from Word */
+static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
+{
+ TCGv_i64 ax, bx;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+ bx = tcg_temp_new_i64();
+
+ gen_load_gpr(ax, a->rs);
+ gen_load_gpr(bx, a->rt);
+ gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
+
+ tcg_temp_free(bx);
+ tcg_temp_free(ax);
+
+ return true;
+}
+
/* Parallel Extend Upper from Word */
static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
{
--
2.31.1
- [PULL 00/19] MIPS patches for 2021-07-11, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 01/19] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 02/19] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 05/19] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower),
Philippe Mathieu-Daudé <=
- [PULL 07/19] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 08/19] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 09/19] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 10/19] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 13/19] target/mips: Rewrite UHI errno_mips() using switch statement, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 14/19] dp8393x: fix CAM descriptor entry index, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 15/19] dp8393x: Replace address_space_rw(is_write=1) by address_space_write(), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 16/19] dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition, Philippe Mathieu-Daudé, 2021/07/11