[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs |
Date: |
Wed, 25 Aug 2021 15:01:46 +0200 |
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1
opcodes to decodetree") we misplaced the decoder call. Move
it to the correct place.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6b95cca052a..490add3fc15 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16094,6 +16094,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
/* Transition to the auto-generated decoder. */
+ /* Vendor specific extensions */
+ if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx,
ctx->opcode)) {
+ return;
+ }
+
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
return;
@@ -16103,9 +16108,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx,
ctx->opcode)) {
return;
}
- if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx,
ctx->opcode)) {
- return;
- }
if (decode_opc_legacy(env, ctx)) {
return;
--
2.31.1
- [PULL 00/28] MIPS patches for 2021-08-25, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 01/28] target/mips: Remove JR opcode unused arguments, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 02/28] target/mips: Simplify PREF opcode, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs,
Philippe Mathieu-Daudé <=
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 05/28] target/mips: Rename 'rtype' as 'r', Philippe Mathieu-Daudé, 2021/08/25
- [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25