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[PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension |
Date: |
Wed, 25 Aug 2021 15:01:52 +0200 |
The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801235926.3178085-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/vr54xx.decode | 8 ++++++++
target/mips/tcg/translate.c | 3 +++
target/mips/tcg/vr54xx_translate.c | 19 +++++++++++++++++++
target/mips/tcg/meson.build | 2 ++
5 files changed, 33 insertions(+)
create mode 100644 target/mips/tcg/vr54xx.decode
create mode 100644 target/mips/tcg/vr54xx_translate.c
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 791e3e2c7e8..bb0a6b8d74f 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -201,6 +201,7 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
#endif
+bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
/*
* Helpers for implementing sets of trans_* functions.
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode
new file mode 100644
index 00000000000..f6b3e42c999
--- /dev/null
+++ b/target/mips/tcg/vr54xx.decode
@@ -0,0 +1,8 @@
+# MIPS VR5432 instruction set extensions
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: VR5432 Microprocessor User’s Manual
+# (Document Number U13751EU5V0UM00)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 490add3fc15..34363639937 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16098,6 +16098,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx,
ctx->opcode)) {
return;
}
+ if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx,
ctx->opcode)) {
+ return;
+ }
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
diff --git a/target/mips/tcg/vr54xx_translate.c
b/target/mips/tcg/vr54xx_translate.c
new file mode 100644
index 00000000000..13e58fdd8df
--- /dev/null
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -0,0 +1,19 @@
+/*
+ * VR5432 extensions translation routines
+ *
+ * Reference: VR5432 Microprocessor User’s Manual
+ * (Document Number U13751EU5V0UM00)
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+#include "internal.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-vr54xx.c.inc"
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index ff618a159b7..8f6f7508b66 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -2,6 +2,7 @@
decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
+ decodetree.process('vr54xx.decode', extra_args:
'--decode=decode_ext_vr54xx'),
]
mips_ss.add(gen)
@@ -19,6 +20,7 @@
'translate_addr_const.c',
'txx9_translate.c',
'vr54xx_helper.c',
+ 'vr54xx_translate.c',
))
mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
--
2.31.1
- [PULL 00/28] MIPS patches for 2021-08-25, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 01/28] target/mips: Remove JR opcode unused arguments, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 02/28] target/mips: Simplify PREF opcode, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 05/28] target/mips: Rename 'rtype' as 'r', Philippe Mathieu-Daudé, 2021/08/25
- [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension,
Philippe Mathieu-Daudé <=
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25