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[PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i() |
Date: |
Wed, 25 Aug 2021 15:02:01 +0200 |
$rt register is used read-only, so we can replace tcg_const_i32()
temporary by tcg_constant_i32().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>
---
target/mips/tcg/translate.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 4b689a54abb..a6df9beb670 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -9072,12 +9072,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext
*ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- {
- TCGv_i32 fs_tmp = tcg_const_i32(rd);
-
- gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
- tcg_temp_free_i32(fs_tmp);
- }
+ gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt);
/* Stop translation as we may have changed hflags */
ctx->base.is_jmp = DISAS_STOP;
break;
@@ -9694,12 +9689,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int
rt, int fs)
case OPC_CTC1:
gen_load_gpr(t0, rt);
save_cpu_state(ctx, 0);
- {
- TCGv_i32 fs_tmp = tcg_const_i32(fs);
-
- gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
- tcg_temp_free_i32(fs_tmp);
- }
+ gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt);
/* Stop translation as we may have changed hflags */
ctx->base.is_jmp = DISAS_STOP;
break;
--
2.31.1
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, (continued)
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(),
Philippe Mathieu-Daudé <=
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 21/28] target/mips: Inline gen_helper_0e0i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 23/28] target/mips: Define gen_helper() macros in translate.h, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 25/28] target/mips: Replace GET_LMASK() macro by get_lmask(32) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 26/28] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 27/28] target/mips: Store CP0_Config0 in DisasContext, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 28/28] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian(), Philippe Mathieu-Daudé, 2021/08/25