[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension
From: |
Alistair Francis |
Subject: |
Re: [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension |
Date: |
Mon, 30 Aug 2021 15:11:33 +1000 |
On Thu, Aug 26, 2021 at 3:08 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zbc:
> - clmul
> - clmulh
> - clmulr
>
> Note that these instructions were already defined in the pre-0.93 and
> the 0.93 draft-B proposals, but had not been omitted in the earlier
> addition of draft-B to QEmu.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> Changes in v6:
> - Move gen_clmulh to trans_rvb.c.inc, as per Richard H's request.
>
> Changes in v5:
> - Introduce gen_clmulh (as suggested by Richard H) and use to simplify
> trans_clmulh().
>
> Changes in v3:
> - This adds the Zbc instructions as a spearate commit.
> - Uses a helper for clmul/clmulr instead of inlining the calculation of
> the result (addressing a comment from Richard Henderson).
>
> target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++
> target/riscv/helper.h | 2 ++
> target/riscv/insn32.decode | 5 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
> 4 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
> index 5b2f795d03..73be5a81c7 100644
> --- a/target/riscv/bitmanip_helper.c
> +++ b/target/riscv/bitmanip_helper.c
> @@ -3,6 +3,7 @@
> *
> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong
> rs2)
> {
> return do_gorc(rs1, rs2, 32);
> }
> +
> +target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
> +{
> + target_ulong result = 0;
> +
> + for (int i = 0; i < TARGET_LONG_BITS; i++) {
> + if ((rs2 >> i) & 1) {
> + result ^= (rs1 << i);
> + }
> + }
> +
> + return result;
> +}
> +
> +target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
> +{
> + target_ulong result = 0;
> +
> + for (int i = 0; i < TARGET_LONG_BITS; i++) {
> + if ((rs2 >> i) & 1) {
> + result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
> + }
> + }
> +
> + return result;
> +}
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 415e37bc37..c559c860a7 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>
> /* Special functions */
> DEF_HELPER_3(csrrw, tl, env, tl, tl)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 1166e7f648..04711111c8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -713,6 +713,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
> greviw 0110100 .......... 101 ..... 0011011 @sh5
> gorciw 0010100 .......... 101 ..... 0011011 @sh5
>
> +# *** RV32 Zbc Standard Extension ***
> +clmul 0000101 .......... 001 ..... 0110011 @r
> +clmulh 0000101 .......... 011 ..... 0110011 @r
> +clmulr 0000101 .......... 010 ..... 0110011 @r
> +
> # *** RV32 Zbs Standard Extension ***
> bclr 0100100 .......... 001 ..... 0110011 @r
> bclri 01001. ........... 001 ..... 0010011 @sh
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 21d713df27..6a3e0c6a09 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
> + * RISC-V translation routines for the Zb[acs] Standard Extension.
> *
> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> @@ -24,6 +24,12 @@
> } \
> } while (0)
>
> +#define REQUIRE_ZBC(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
> + return false; \
> + } \
> +} while (0)
> +
> #define REQUIRE_ZBS(ctx) do { \
> if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
> return false; \
> @@ -357,3 +363,27 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw
> *a)
> tcg_temp_free(source1);
> return true;
> }
> +
> +static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_helper_clmul);
> +}
> +
> +static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
> +{
> + gen_helper_clmulr(dst, src1, src2);
> + tcg_gen_shri_tl(dst, dst, 1);
> +}
> +
> +static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_clmulh);
> +}
> +
> +static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_helper_clmulr);
> +}
> --
> 2.25.1
>
>
- Re: [PATCH v6 02/14] target/riscv: Reassign instructions to the Zba-extension, (continued)
- [PATCH v6 04/14] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/08/25
- [PATCH v6 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/08/25
- [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/08/25
- [PATCH v6 06/14] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/25
- Re: [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension,
Alistair Francis <=
- [PATCH v6 08/14] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 11/14] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/08/25
- [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/25
- [PATCH v6 13/14] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/08/25
- [PATCH v6 14/14] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/08/25
- [PATCH v6 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/08/25