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Re: [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro |
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Date: |
Mon, 30 Aug 2021 15:16:28 +1000 |
On Thu, Aug 26, 2021 at 3:15 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> With the changes to Zb[abcs], there's some encodings that are
> different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
> we'll need a helper macro allowing us to select on RV32, as well.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Moved the REQUIRE_32BIT macro into a separate commit.
>
> target/riscv/translate.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5c099ff007..aabdd44663 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -417,6 +417,12 @@ EX_SH(12)
> } \
> } while (0)
>
> +#define REQUIRE_32BIT(ctx) do { \
> + if (!is_32bit(ctx)) { \
> + return false; \
> + } \
> +} while (0)
> +
> #define REQUIRE_64BIT(ctx) do { \
> if (is_32bit(ctx)) { \
> return false; \
> --
> 2.25.1
>
>
- Re: [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, (continued)
- [PATCH v6 06/14] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 08/14] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 11/14] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/08/25
- [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/25
- Re: [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro,
Alistair Francis <=
- [PATCH v6 13/14] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/08/25
- [PATCH v6 14/14] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/08/25
- [PATCH v6 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/08/25
- [PATCH v6 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/08/25