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Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

From: Richard Henderson
Subject: Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO
Date: Mon, 1 Nov 2021 14:04:03 -0400
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/1/21 1:55 PM, Peter Maydell wrote:
On Tue, 26 Oct 2021 at 17:22, Richard Henderson
<richard.henderson@linaro.org> wrote:

On 10/26/21 12:12 AM, Alexander Graf wrote:
+        if (cm) {
+            /* We don't cache MMIO regions */
+            advance_pc = true;
+            break;
+        }

The assert should come first.  If the "iss valid" bit is not set, then nothing 
else in the
word is defined.

No, ISV only indicates that ISS[23:14] is valid; ISS[13:0] (including CM)
are valid regardless. (The distinction is that the bits which might or
might not be valid are the ones which encode information about the insn
necessary to possibly emulate it, like the data access size and the
source/destination register; the always-present ones are the ones that
have always been reported for data aborts -- AArch32 DFSR has a CM bit,
for instance.)

Thanks, that clears up some of my confusion here and a bit further downthread.


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