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[PULL 06/41] target/mips: Adjust style in msa_translate_init()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 06/41] target/mips: Adjust style in msa_translate_init() |
Date: |
Tue, 2 Nov 2021 14:42:05 +0100 |
While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211023214803.522078-34-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..3aa15e147c2 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -280,13 +280,15 @@ void msa_translate_init(void)
int i;
for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+ int off;
/*
* The MSA vector registers are mapped on the
* scalar floating-point unit (FPU) registers.
*/
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
msa_wr_d[i * 2] = fpu_f64[i];
+
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.31.1
- [PULL 00/41] MIPS patches for 2021-11-02, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 04/41] target/mips: Fix MSA MADDV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 06/41] target/mips: Adjust style in msa_translate_init(),
Philippe Mathieu-Daudé <=
- [PULL 07/41] target/mips: Use dup_const() to simplify, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 08/41] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 11/41] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 12/41] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02