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[PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum |
Date: |
Tue, 2 Nov 2021 14:42:08 +0100 |
Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-7-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e0ccd8c1cb8..56a0148fec2 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1791,10 +1791,10 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_MULR_Q_df:
case OPC_MADDR_Q_df:
case OPC_MSUBR_Q_df:
- tdf = tcg_constant_i32(df + 1);
+ tdf = tcg_constant_i32(DF_HALF + df);
break;
default:
- tdf = tcg_constant_i32(df + 2);
+ tdf = tcg_constant_i32(DF_WORD + df);
break;
}
@@ -2023,7 +2023,7 @@ static void gen_msa_2rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
/* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(df + 2);
+ TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
switch (MASK_MSA_2RF(ctx->opcode)) {
case OPC_FCLASS_df:
--
2.31.1
- [PULL 00/41] MIPS patches for 2021-11-02, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 04/41] target/mips: Fix MSA MADDV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 06/41] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 07/41] target/mips: Use dup_const() to simplify, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 08/41] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum,
Philippe Mathieu-Daudé <=
- [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 11/41] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 12/41] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 19/41] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02