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[PULL 08/41] target/mips: Have check_msa_access() return a boolean
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 08/41] target/mips: Have check_msa_access() return a boolean |
Date: |
Tue, 2 Nov 2021 14:42:07 +0100 |
Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled (the instruction got
decoded properly, but we raised an exception).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b135c58fd4f..e0ccd8c1cb8 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -295,19 +295,24 @@ void msa_translate_init(void)
}
}
-static inline int check_msa_access(DisasContext *ctx)
+/*
+ * Check if MSA is enabled.
+ * This function is always called with MSA available.
+ * If MSA is disabled, raise an exception.
+ */
+static inline bool check_msa_enabled(DisasContext *ctx)
{
if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
!(ctx->hflags & MIPS_HFLAG_F64))) {
gen_reserved_instruction(ctx);
- return 0;
+ return false;
}
if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
+ return false;
}
- return 1;
+ return true;
}
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
@@ -339,7 +344,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int
s16, TCGCond cond)
{
TCGv_i64 t0;
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
@@ -371,7 +378,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
if_not)
{
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
@@ -2143,7 +2152,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
uint32_t opcode = ctx->opcode;
- check_msa_access(ctx);
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
switch (MASK_MSA_MINOR(opcode)) {
case OPC_MSA_I8_00:
--
2.31.1
- [PULL 00/41] MIPS patches for 2021-11-02, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 04/41] target/mips: Fix MSA MADDV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 06/41] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 07/41] target/mips: Use dup_const() to simplify, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 08/41] target/mips: Have check_msa_access() return a boolean,
Philippe Mathieu-Daudé <=
- [PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 11/41] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 12/41] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02