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Re: [PATCH v1 4/9] hw/dma: Add the DMA control interface
From: |
Edgar E. Iglesias |
Subject: |
Re: [PATCH v1 4/9] hw/dma: Add the DMA control interface |
Date: |
Fri, 19 Nov 2021 18:01:50 +0100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Wed, Nov 17, 2021 at 02:18:36PM +0000, Francisco Iglesias wrote:
> Add an interface for controlling DMA models that are reused with other
> models. This allows a controlling model to start transfers through the
> DMA while reusing the DMA's handling of transfer state and completion
> signaling.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> hw/dma/dma-ctrl.c | 31 ++++++++++++++++++++
> hw/dma/meson.build | 1 +
> include/hw/dma/dma-ctrl.h | 74
> +++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 106 insertions(+)
> create mode 100644 hw/dma/dma-ctrl.c
> create mode 100644 include/hw/dma/dma-ctrl.h
>
> diff --git a/hw/dma/dma-ctrl.c b/hw/dma/dma-ctrl.c
> new file mode 100644
> index 0000000000..4a9b68dac1
> --- /dev/null
> +++ b/hw/dma/dma-ctrl.c
> @@ -0,0 +1,31 @@
> +/*
> + * DMA control interface.
> + *
> + * Copyright (c) 2021 Xilinx Inc.
> + * Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +#include "hw/dma/dma-ctrl.h"
> +
> +void dma_ctrl_read_with_notify(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t len,
> + DmaCtrlNotify *notify, bool start_dma)
> +{
> + DmaCtrlClass *dcc = DMA_CTRL_GET_CLASS(dma_ctrl);
> + dcc->read(dma_ctrl, addr, len, notify, start_dma);
> +}
> +
> +static const TypeInfo dma_ctrl_info = {
> + .name = TYPE_DMA_CTRL,
> + .parent = TYPE_INTERFACE,
> + .class_size = sizeof(DmaCtrlClass),
> +};
> +
> +static void dma_ctrl_register_types(void)
> +{
> + type_register_static(&dma_ctrl_info);
> +}
> +
> +type_init(dma_ctrl_register_types)
> diff --git a/hw/dma/meson.build b/hw/dma/meson.build
> index f3f0661bc3..c0bc134046 100644
> --- a/hw/dma/meson.build
> +++ b/hw/dma/meson.build
> @@ -14,3 +14,4 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true:
> files('pxa2xx_dma.c'))
> softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
> softmmu_ss.add(when: 'CONFIG_XLNX_CSU_DMA', if_true: files('xlnx_csu_dma.c'))
> +common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('dma-ctrl.c'))
> diff --git a/include/hw/dma/dma-ctrl.h b/include/hw/dma/dma-ctrl.h
> new file mode 100644
> index 0000000000..498469395f
> --- /dev/null
> +++ b/include/hw/dma/dma-ctrl.h
> @@ -0,0 +1,74 @@
> +/*
> + * DMA control interface.
> + *
> + * Copyright (c) 2021 Xilinx Inc.
> + * Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef HW_DMA_CTRL_H
> +#define HW_DMA_CTRL_H
> +
> +#include "qemu-common.h"
> +#include "hw/hw.h"
> +#include "qom/object.h"
> +
> +#define TYPE_DMA_CTRL "dma-ctrl"
> +
> +#define DMA_CTRL_CLASS(klass) \
> + OBJECT_CLASS_CHECK(DmaCtrlClass, (klass), TYPE_DMA_CTRL)
> +#define DMA_CTRL_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(DmaCtrlClass, (obj), TYPE_DMA_CTRL)
> +#define DMA_CTRL(obj) \
> + INTERFACE_CHECK(DmaCtrl, (obj), TYPE_DMA_CTRL)
> +
> +typedef void (*dmactrl_notify_fn)(void *opaque);
> +
> +typedef struct DmaCtrlNotify {
> + void *opaque;
> + dmactrl_notify_fn cb;
> +} DmaCtrlNotify;
> +
> +typedef struct DmaCtrl {
> + Object Parent;
> +} DmaCtrl;
> +
> +typedef struct DmaCtrlClass {
> + InterfaceClass parent;
> +
> + /*
> + * read: Start a read transfer on the DMA implementing the DMA control
> + * interface
> + *
> + * @dma_ctrl: the DMA implementing this interface
> + * @addr: the address to read
> + * @len: the amount of bytes to read at 'addr'
> + * @notify: the structure containg a callback to call and opaque pointer
> + * to pass the callback when the transfer has been completed
> + * @start_dma: true for starting the DMA transfer and false for just
> + * refilling and proceding an already started transfer
> + */
> + void (*read)(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t len,
> + DmaCtrlNotify *notify, bool start_dma);
> +} DmaCtrlClass;
> +
> +/*
> + * Start a read transfer on a DMA implementing the DMA control interface.
> + * The DMA will notify the caller that 'len' bytes have been read at 'addr'
> + * through the callback in the DmaCtrlNotify structure. For allowing
> refilling
> + * an already started transfer the DMA notifies the caller before considering
> + * the transfer done (e.g. before setting done flags, generating IRQs and
> + * modifying other relevant internal device state).
> + *
> + * @dma_ctrl: the DMA implementing this interface
> + * @addr: the address to read
> + * @len: the amount of bytes to read at 'addr'
> + * @notify: the structure containing a callback to call and opaque pointer
> + * to pass the callback when the transfer has been completed
> + * @start_dma: true for starting the DMA transfer and false for just
> + * refilling and proceding an already started transfer
> + */
> +void dma_ctrl_read_with_notify(DmaCtrl *dma_ctrl, hwaddr addr, uint32_t len,
> + DmaCtrlNotify *notify, bool start_dma);
> +
> +#endif /* HW_DMA_CTRL_H */
> --
> 2.11.0
>
- [PATCH v1 0/9] Xilinx Versal's PMC SLCR and OSPI support, Francisco Iglesias, 2021/11/17
- [PATCH v1 2/9] hw/arm/xlnx-versal: Connect Versal's PMC SLCR, Francisco Iglesias, 2021/11/17
- [PATCH v1 1/9] hw/misc: Add a model of Versal's PMC SLCR, Francisco Iglesias, 2021/11/17
- [PATCH v1 3/9] include/hw/dma/xlnx_csu_dma: Include ptimer.h and stream.h in the header, Francisco Iglesias, 2021/11/17
- [PATCH v1 4/9] hw/dma: Add the DMA control interface, Francisco Iglesias, 2021/11/17
- Re: [PATCH v1 4/9] hw/dma: Add the DMA control interface,
Edgar E. Iglesias <=
- [PATCH v1 9/9] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI, Francisco Iglesias, 2021/11/17
- [PATCH v1 5/9] hw/dma/xlnx_csu_dma: Implement the DMA control interface, Francisco Iglesias, 2021/11/17
- [PATCH v1 7/9] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model, Francisco Iglesias, 2021/11/17
- [PATCH v1 8/9] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g, Francisco Iglesias, 2021/11/17
- [PATCH v1 6/9] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller, Francisco Iglesias, 2021/11/17