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Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-sof
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles |
Date: |
Thu, 25 Nov 2021 21:47:28 +1000 |
On Wed, Nov 24, 2021 at 5:33 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Frédéric,
>
> On 11/24/21 07:55, Frédéric Pétrot wrote:
> > On 24/11/2021 07:12, Alistair Francis wrote:
> >> On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
> >> <frederic.petrot@univ-grenoble-alpes.fr> wrote:
> >>>
> >>> This patch is kind of a mess because several files have to be slightly
> >>> modified to allow for a new target. In the current status, we have done
> >>> our best to have RV64 and RV128 under the same RV64 umbrella, but there
> >>> is still work to do to have a single executable for both.
> >>> In particular, we have no atomic accesses for aligned 128-bit addresses.
> >>>
> >>> Once this patch applied, adding risc128-sofmmu to --target-list produces
> >>> a (no so useful yet) executable.
> >>
> >> I can't remember if we discussed this before, but do we need the
> >> riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
> >> executable?
> >
> > Hello Alistair,
> > Richard was also advocating for a single executable, but pointed out that
> > we need to disable mttcg because there is a need for specific tcg
> > support for
> > 128-bit aligned atomics.
> > Given my understanding of that part of QEMU, I choose the easy way to
> > disable
> > it once and for all at compile time until we have that.
>
>
> In rv128_base_cpu_init():
>
> if (qemu_tcg_mttcg_enabled) {
> /* Missing 128-bit aligned atomics */
> error_report("128-bit RISC-V currently does not work"
> " with Multi Threaded TCG. Please use:"
> " -accel tcg,thread=single");
> exit(EXIT_FAILURE);
> }
That seems like a good option! I think we could add this to the CPU
realise function.
The problem with a riscv128-sofmmu executable is that it's hard to get
rid of in the future. We are very slowly moving towards a single
executable and adding a new one means we are stuck with it for a
while.
Alistair
>
> Regards,
>
> Phil.
- [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, (continued)
[PATCH v5 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/11/12
[PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/11/12
[PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/11/12
[PATCH v5 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/12
[PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/12