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[PULL 45/61] target/riscv: Extend pc for runtime pc write
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From: |
Alistair Francis |
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Subject: |
[PULL 45/61] target/riscv: Extend pc for runtime pc write |
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Date: |
Fri, 21 Jan 2022 15:58:14 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 736cf1d4e7..eac5f7bf03 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -355,7 +355,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = value;
+
+ if (env->xl == MXL_RV32) {
+ env->pc = (int32_t)value;
+ } else {
+ env->pc = value;
+ }
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -363,7 +368,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = tb->pc;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
}
static bool riscv_cpu_has_work(CPUState *cs)
@@ -384,7 +395,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
- env->pc = data[0];
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)data[0];
+ } else {
+ env->pc = data[0];
+ }
}
static void riscv_cpu_reset(DeviceState *dev)
--
2.31.1
- [PULL 38/61] roms/opensbi: Remove ELF images, (continued)
- [PULL 38/61] roms/opensbi: Remove ELF images, Alistair Francis, 2022/01/21
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 2022/01/21
- [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl, Alistair Francis, 2022/01/21
- [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios, Alistair Francis, 2022/01/21
- [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names, Alistair Francis, 2022/01/21
- [PULL 40/61] target/riscv: Don't save pc when exception return, Alistair Francis, 2022/01/21
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr, Alistair Francis, 2022/01/21
- [PULL 43/61] target/riscv: Create xl field in env, Alistair Francis, 2022/01/21
- [PULL 42/61] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 2022/01/21
- [PULL 44/61] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 2022/01/21
- [PULL 45/61] target/riscv: Extend pc for runtime pc write,
Alistair Francis <=
- [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN, Alistair Francis, 2022/01/21
- [PULL 55/61] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2022/01/21
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only, Alistair Francis, 2022/01/21
- [PULL 57/61] target/riscv: Adjust vector address with mask, Alistair Francis, 2022/01/21
- [PULL 59/61] target/riscv: Set default XLEN for hypervisor, Alistair Francis, 2022/01/21
- [PULL 61/61] target/riscv: Relax UXL field for debugging, Alistair Francis, 2022/01/21
- [PULL 60/61] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/21