[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 54/61] target/riscv: Adjust vsetvl according to XLEN
From: |
Alistair Francis |
Subject: |
[PULL 54/61] target/riscv: Adjust vsetvl according to XLEN |
Date: |
Fri, 21 Jan 2022 15:58:23 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/vector_helper.c | 7 +++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6c740b92c1..fe58ccaeae 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -491,6 +491,11 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
}
#endif
+static inline int riscv_cpu_xlen(CPURISCVState *env)
+{
+ return 16 << env->xl;
+}
+
/*
* Encode LMUL to lmul as follows:
* LMUL vlmul lmul
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a9484c22ea..8b7c9ec890 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -36,8 +36,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
- bool vill = FIELD_EX64(s2, VTYPE, VILL);
- target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
+ int xlen = riscv_cpu_xlen(env);
+ bool vill = (s2 >> (xlen - 1)) & 0x1;
+ target_ulong reserved = s2 &
+ MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
/* Fractional LMUL. */
--
2.31.1
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, (continued)
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 2022/01/21
- [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl, Alistair Francis, 2022/01/21
- [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios, Alistair Francis, 2022/01/21
- [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names, Alistair Francis, 2022/01/21
- [PULL 40/61] target/riscv: Don't save pc when exception return, Alistair Francis, 2022/01/21
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr, Alistair Francis, 2022/01/21
- [PULL 43/61] target/riscv: Create xl field in env, Alistair Francis, 2022/01/21
- [PULL 42/61] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 2022/01/21
- [PULL 44/61] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 2022/01/21
- [PULL 45/61] target/riscv: Extend pc for runtime pc write, Alistair Francis, 2022/01/21
- [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN,
Alistair Francis <=
- [PULL 55/61] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2022/01/21
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only, Alistair Francis, 2022/01/21
- [PULL 57/61] target/riscv: Adjust vector address with mask, Alistair Francis, 2022/01/21
- [PULL 59/61] target/riscv: Set default XLEN for hypervisor, Alistair Francis, 2022/01/21
- [PULL 61/61] target/riscv: Relax UXL field for debugging, Alistair Francis, 2022/01/21
- [PULL 60/61] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/21
- [PULL 53/61] target/riscv: Split out the vill from vtype, Alistair Francis, 2022/01/21