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[PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush
From: |
Richard Henderson |
Subject: |
[PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush |
Date: |
Fri, 11 Feb 2022 12:30:31 +1100 |
From: Idan Horowitz <idan.horowitz@gmail.com>
When the length of the range is large enough, clearing the whole cache is
faster than iterating over the (possibly extremely large) set of pages
contained in the range.
This mimics the pre-existing similar optimization done on the flush of the
tlb itself.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 5e0d0eebc3..926d9a9192 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -783,6 +783,15 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu,
}
qemu_spin_unlock(&env_tlb(env)->c.lock);
+ /*
+ * If the length is larger than the jump cache size, then it will take
+ * longer to clear each entry individually than it will to clear it all.
+ */
+ if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) {
+ cpu_tb_jmp_cache_clear(cpu);
+ return;
+ }
+
for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) {
tb_flush_jmp_cache(cpu, d.addr + i);
}
--
2.25.1
- [PULL 00/34] tcg patch queue, Richard Henderson, 2022/02/10
- [PULL 01/34] common-user/host/sparc64: Fix safe_syscall_base, Richard Henderson, 2022/02/10
- [PULL 02/34] linux-user: Introduce host_signal_mask, Richard Henderson, 2022/02/10
- [PULL 03/34] linux-user: Introduce host_sigcontext, Richard Henderson, 2022/02/10
- [PULL 05/34] linux-user/include/host/sparc64: Fix host_sigcontext, Richard Henderson, 2022/02/10
- [PULL 04/34] linux-user: Move sparc/host-signal.h to sparc64/host-signal.h, Richard Henderson, 2022/02/10
- [PULL 11/34] tcg/aarch64: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 07/34] softmmu/cpus: Check if the cpu work list is empty atomically, Richard Henderson, 2022/02/10
- [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB, Richard Henderson, 2022/02/10
- [PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush,
Richard Henderson <=
- [PULL 10/34] tcg/i386: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 09/34] tcg/loongarch64: Fix fallout from recent MO_Q renaming, Richard Henderson, 2022/02/10
- [PULL 12/34] tcg/ppc: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 15/34] tcg/tci: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 14/34] tcg/s390x: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 13/34] tcg/riscv: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 17/34] tcg/arm: Drop support for armv4 and armv5 hosts, Richard Henderson, 2022/02/10
- [PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 18/34] tcg/arm: Remove use_armv5t_instructions, Richard Henderson, 2022/02/10
- [PULL 19/34] tcg/arm: Remove use_armv6_instructions, Richard Henderson, 2022/02/10