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[PULL 18/34] tcg/arm: Remove use_armv5t_instructions
From: |
Richard Henderson |
Subject: |
[PULL 18/34] tcg/arm: Remove use_armv5t_instructions |
Date: |
Fri, 11 Feb 2022 12:30:43 +1100 |
This is now always true, since we require armv6.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 3 +--
tcg/arm/tcg-target.c.inc | 35 ++++++-----------------------------
2 files changed, 7 insertions(+), 31 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index f41b809554..5c9ba5feea 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -28,7 +28,6 @@
extern int arm_arch;
-#define use_armv5t_instructions (__ARM_ARCH >= 5 || arm_arch >= 5)
#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
@@ -109,7 +108,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
+#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 29d63e98a8..f3b635063f 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -596,11 +596,7 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond,
TCGReg rn)
* Unless the C portion of QEMU is compiled as thumb, we don't need
* true BX semantics; merely a branch to an address held in a register.
*/
- if (use_armv5t_instructions) {
- tcg_out_bx_reg(s, cond, rn);
- } else {
- tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);
- }
+ tcg_out_bx_reg(s, cond, rn);
}
static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
@@ -1247,14 +1243,7 @@ static void tcg_out_goto(TCGContext *s, ARMCond cond,
const tcg_insn_unit *addr)
}
/* LDR is interworking from v5t. */
- if (arm_mode || use_armv5t_instructions) {
- tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
- return;
- }
-
- /* else v4t */
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
- tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP);
+ tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
}
/*
@@ -1270,26 +1259,14 @@ static void tcg_out_call(TCGContext *s, const
tcg_insn_unit *addr)
if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
if (arm_mode) {
tcg_out_bl_imm(s, COND_AL, disp);
- return;
- }
- if (use_armv5t_instructions) {
+ } else {
tcg_out_blx_imm(s, disp);
- return;
}
+ return;
}
- if (use_armv5t_instructions) {
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
- tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP);
- } else if (arm_mode) {
- /* ??? Know that movi_pool emits exactly 1 insn. */
- tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC);
- tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
- } else {
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
- tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC);
- tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP);
- }
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
+ tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP);
}
static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l)
--
2.25.1
- [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB, (continued)
- [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB, Richard Henderson, 2022/02/10
- [PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush, Richard Henderson, 2022/02/10
- [PULL 10/34] tcg/i386: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 09/34] tcg/loongarch64: Fix fallout from recent MO_Q renaming, Richard Henderson, 2022/02/10
- [PULL 12/34] tcg/ppc: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 15/34] tcg/tci: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 14/34] tcg/s390x: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 13/34] tcg/riscv: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 17/34] tcg/arm: Drop support for armv4 and armv5 hosts, Richard Henderson, 2022/02/10
- [PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 18/34] tcg/arm: Remove use_armv5t_instructions,
Richard Henderson <=
- [PULL 19/34] tcg/arm: Remove use_armv6_instructions, Richard Henderson, 2022/02/10
- [PULL 21/34] tcg/arm: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 20/34] tcg/arm: Check alignment for ldrd and strd, Richard Henderson, 2022/02/10
- [PULL 22/34] tcg/arm: Reserve a register for guest_base, Richard Henderson, 2022/02/10
- [PULL 23/34] tcg/arm: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 24/34] tcg/mips: Support unaligned access for user-only, Richard Henderson, 2022/02/10
- [PULL 25/34] tcg/mips: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 28/34] tcg/sparc: Add scratch argument to tcg_out_movi_int, Richard Henderson, 2022/02/10
- [PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants, Richard Henderson, 2022/02/10
- [PULL 27/34] tcg/sparc: Split out tcg_out_movi_imm32, Richard Henderson, 2022/02/10