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[PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only
From: |
Richard Henderson |
Subject: |
[PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only |
Date: |
Fri, 11 Feb 2022 12:30:41 +1100 |
From: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220106134238.3936163-1-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.h | 2 -
tcg/loongarch64/tcg-target.c.inc | 71 +++++++++++++++++++++++++++++++-
2 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 05010805e7..d58a6162f2 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -171,9 +171,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t,
uintptr_t, uintptr_t);
#define TCG_TARGET_DEFAULT_MO (0)
-#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
-#endif
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d31a0e5991..a3debf6da7 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -29,6 +29,8 @@
* THE SOFTWARE.
*/
+#include "../tcg-ldst.c.inc"
+
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"zero",
@@ -642,8 +644,6 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg
val,
*/
#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.c.inc"
-
/*
* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* MemOpIdx oi, uintptr_t ra)
@@ -825,6 +825,61 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
return tcg_out_goto(s, l->raddr);
}
+#else
+
+/*
+ * Alignment helpers for user-mode emulation
+ */
+
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
+ unsigned a_bits)
+{
+ TCGLabelQemuLdst *l = new_ldst_label(s);
+
+ l->is_ld = is_ld;
+ l->addrlo_reg = addr_reg;
+
+ /*
+ * Without micro-architecture details, we don't know which of bstrpick or
+ * andi is faster, so use bstrpick as it's not constrained by imm field
+ * width. (Not to say alignments >= 2^12 are going to happen any time
+ * soon, though)
+ */
+ tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
+
+ l->label_ptr[0] = s->code_ptr;
+ tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
+
+ l->raddr = tcg_splitwx_to_rx(s->code_ptr);
+}
+
+static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ /* resolve label address */
+ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
+
+ /* tail call, with the return address back inline. */
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr);
+ tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld
+ : helper_unaligned_st), true);
+ return true;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
#endif /* CONFIG_SOFTMMU */
/*
@@ -887,6 +942,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, TCGType type)
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
+#else
+ unsigned a_bits;
#endif
TCGReg base;
@@ -903,6 +960,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, TCGType type)
data_regl, addr_regl,
s->code_ptr, label_ptr);
#else
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, true, addr_regl, a_bits);
+ }
base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type);
@@ -941,6 +1002,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args)
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
+#else
+ unsigned a_bits;
#endif
TCGReg base;
@@ -958,6 +1021,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args)
data_regl, addr_regl,
s->code_ptr, label_ptr);
#else
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, false, addr_regl, a_bits);
+ }
base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc);
--
2.25.1
- [PULL 07/34] softmmu/cpus: Check if the cpu work list is empty atomically, (continued)
- [PULL 07/34] softmmu/cpus: Check if the cpu work list is empty atomically, Richard Henderson, 2022/02/10
- [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB, Richard Henderson, 2022/02/10
- [PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush, Richard Henderson, 2022/02/10
- [PULL 10/34] tcg/i386: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 09/34] tcg/loongarch64: Fix fallout from recent MO_Q renaming, Richard Henderson, 2022/02/10
- [PULL 12/34] tcg/ppc: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 15/34] tcg/tci: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 14/34] tcg/s390x: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 13/34] tcg/riscv: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 17/34] tcg/arm: Drop support for armv4 and armv5 hosts, Richard Henderson, 2022/02/10
- [PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only,
Richard Henderson <=
- [PULL 18/34] tcg/arm: Remove use_armv5t_instructions, Richard Henderson, 2022/02/10
- [PULL 19/34] tcg/arm: Remove use_armv6_instructions, Richard Henderson, 2022/02/10
- [PULL 21/34] tcg/arm: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 20/34] tcg/arm: Check alignment for ldrd and strd, Richard Henderson, 2022/02/10
- [PULL 22/34] tcg/arm: Reserve a register for guest_base, Richard Henderson, 2022/02/10
- [PULL 23/34] tcg/arm: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 24/34] tcg/mips: Support unaligned access for user-only, Richard Henderson, 2022/02/10
- [PULL 25/34] tcg/mips: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 28/34] tcg/sparc: Add scratch argument to tcg_out_movi_int, Richard Henderson, 2022/02/10
- [PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants, Richard Henderson, 2022/02/10